CA1214565A - Method of operating a data processing system via depictor-linked microcode and logic circuitry - Google Patents
Method of operating a data processing system via depictor-linked microcode and logic circuitryInfo
- Publication number
- CA1214565A CA1214565A CA000462175A CA462175A CA1214565A CA 1214565 A CA1214565 A CA 1214565A CA 000462175 A CA000462175 A CA 000462175A CA 462175 A CA462175 A CA 462175A CA 1214565 A CA1214565 A CA 1214565A
- Authority
- CA
- Canada
- Prior art keywords
- activity
- depictor
- type
- instruction
- microcode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
- G06F9/4486—Formation of subprogram jump address
Abstract
ABSTRACT OF THE DISCLOSURE
METHOD OF OPERATING A DATA PROCESSING SYSTEM VIA
DEPICTOR-LINKED MICROCODE AND LOGIC CIRCUITRY
A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls an activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor;
and activating a low level language microcode program or hardware logic circuit for performing the-called activity if the sensing step detects the second type depictor.
METHOD OF OPERATING A DATA PROCESSING SYSTEM VIA
DEPICTOR-LINKED MICROCODE AND LOGIC CIRCUITRY
A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls an activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor;
and activating a low level language microcode program or hardware logic circuit for performing the-called activity if the sensing step detects the second type depictor.
Description
6~3 METHOD OF OPERATING A DATA pRocEssIrlG SYSTEM
VIA DEPIC.OR-LINKED MICROCODE AND LOGIC CIRCUITRY
BACKGROUND OF THE INVENTION
This invention relates to data processing systems;
and in particular, it relates to methods of operating such systems.
Conventionally, a data processing system is operated by providing a program which consists of a sequence of instructions of some predetermined language These instructions are executed one at a time; and the particular instruction that is currently being executed is pointed to by a program counter.
Each time the execution of an instruction it completed, the program counter is incremented to point Jo the next sequential instruction unless the completed instruction was a UP instruction or a CALL instruction. When a JUMP
instruction is encountered, the program counter is loaded with a new address as the JUMP instruction directs; and then :
instructions are sequentially executed beginning at that Noah address. By comparison, when a CALL instruction is encountered, an independent procedure is executed and then control passes back to the instruction which follows the CALL
instruction.
A procedure is a separate special purpose sequence of instruction-from the same predetermined language of which the program that called it is made up. From the point of view of the calling program, a procedure can be regarded as a single new higher level instruction even though it may be quite complicated and made up of hundreds of instructions from the predetermined language.
By writing a collection of procedures, a programmer can define a new level instruction set. Then programs in the predetermined language can be written which use this new level instruction set by referring to them through the CALL
instruction. Additional details on this prior art method of structuring or partitioning a program are found in the Prentice-Hall textbook entitled Structured Computer Or~lzation by Andrew S. Tanenbaum, 1976, at pages 120-130.
One problem, however, with having a data processing system operate to execute a program which includes several CALL instructions and their corresponding procedures is that the system operates too slowly. This fact and the manner in which the execution speed can be greatly enhanced in accordance with the present invention is explained in detail in the following Detailed Description.
Still another problem with the prior art method of operating a data processing system by means of CALL
instructions and corresponding procedures is that the operation is too inflexible. In particular, the operation is too confined to include special purpose microcode routines or special purpose hardware logic units that perform procedure-like functions.
I
BRIEF SUMMARY OF THE INVASION
Accordingly, a primary object of the invention is to provide an improved method of operating a data processing system.
Another object of the invention is to provide a method of enhancing the speed at which a data processing system operates.
Still another object of the invention is to provide a method of operating a data processing system wherein procedure e functions are performed by low level language microcode routines and hardware logic units.
In the present invention, the above objects and others are achieved by operating a data processing system in a manner which includes the steps of:
storing, in a memory, a software program that contains first and second instructions which respectively call for first and second activities;
linking the first instruction via one type of depict or to a software procedure that performs the first activity, while linking the second instruction via a different type of depict or to a non-software mechanism that performs the second activity;
executing the software program until either the first or second instruction is encountered;
sensing whether the encountered instruction is linked to its activity by the one type or the different type depict or; and executing the procedure if the sensing step dejects the one type depict or; but activating the non-software mechanism if the sensing step detects the different type depict or.
Preferably, the activating step of the non-software mechanism can include the sub step of executing a microcode program to perform the second activity; or alternatively, it includes the sub step of sending parameters to a hardware logic unit to perform the second activity. Also preferably, the depict or in the above-recited method is a partitioned register in winch one portion contains the name of the activity that is to be performed; another portion indicates whether the named activity is implemented via a procedure, a microcode routine, or a hardware logic unit; and another portion indicates how the named activity can be accessed.
BRIEF DESCRIPTION OF THE DRUNKS
Various features and advantages of the invention are described in the following Detailed Description in conjunction with the accompanying drawings wherein:
Figure 1 illustrates one embodiment of a data processing system that is constructed according to the invention;
Figure 2 illustrates the steps that are there taken by the Figure 1 system when a CALM, instruction is executed;
Figure 3 illustrates the details of the hardware components in the computer of the Figure 1 system that are affected by the steps of Figure 2;
Figure 4 illustrates another embodiment of a data processing system that is constructed according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to Figure 1, a data processing system and method of operating the system in accordance with the invention will be described. Included in the Figure 1 system is a digital computer 10 which is coupled to a memory 11 via a bus 12. A software program 13 which computer 10 executes is stored in memory 11.
As used herein, the term "software program" means a sequence of high level language (HULL) instructions with each such instruction being interpreted by a microcode program of low level language (LULL) instructions In turn, the low level language instructions are executed directly by digital logic circuitry in computer 10. Individual high level language instructions in software program 13 are indicated by reference numeral 14; and the low level language microcode programs are indicated by reference numeral 15 in a memory 16.
Three of the illustrated high level language instructions 14 are CALL instructions lea, 14b, and 14c which have been modified to operate in accordance with the present invention. This modified CALL instruction identifies an activity by name, discontinues the execution of the HULL
software program of which it is a part, saves sufficient information to resume execution of the discontinued program at a later time at the point of discontinuance, and initiates the execution of the named activity by passing parameters and control to it.
For example, CALL instruction aye identifies an activity Ax to which control is to be passe along with parameters j and k. Similarly, CALL instruction 14b identifies an activity A to which control is to be passed along with a parameter I And CALL instruction 14c identifies another activity A to which control is to be passed along with parameters m, n, and o.
Each of the activities Ax, Aye and A is either a special purpose software program (ire., a procedure), a special purpose microcode program, or a special purpose hardware logic unit. In each case, the activity is adapted to receive parameters from the CALL instruction, operate on the received parameters in a predetermined fashion, and indicate to the CALL instruction that the operation is complete. For example, one activity may receive the names of several records as parameters from the CALL instruction, -read the identified records from various storage units, and sort them in a predetermined order.
In Figure 1, activity Ax is indicated by reference numeral 20 as being a special purpose procedure of HULL
instructions in memory 11. Those high level language instructions are frown the same language as the instructions which make up program 13. To execute activity Ax the address of the beginning high level language instruction in activity Ax is loaded into a program counter in computer 10; and then instructions from activity Ax are read via the high level language bus 12 into computer 10 where they are interpreted by the microcode programs 15.
By comparison, activity A is indicated by reference numeral 21 in Figure 1 as being a special purpose microcode program in memory 16. Microcode program 21 is made up of a sequence of low level language instructions which are read over a low level language bus 22 into computer 10 where they are executed directly by the computer's digital logic circuitry.
Also as is indicated by reference numeral 23, activity A is comprised of a special purpose logic unit which is coupled via an I/O bus 24 to computer 10. When a CALL
instruction in program 13 is encountered which calls activity A, computer 10 sends the parameters of the CALL instruction to unit 23 via bus 24 and then merely waits for unit 23 to return the results of the operation which the activity performs.
A depict or array 25 is also coupled to the I/O bus 24; and it contains respective depictors for each activity that is called in program 13. thus the Figure 1 array contains three depictors 25-1, 25-2~ and 25-3. By a depict or is herein meant a mechanism which links a named activity to other information which describes how the named activity can be accessed.
In one preferred embodiment, each depict or in array 27 is a content addressable hardware register that is partitioned into three parts, "a", "b". and "c". Part "a"
contains the nave of the activity. Part "b" identifies whether the named activity is a software program in memory 11 or a microcode program in memory 16 or a hardware logic unit on I/O bus 24. And part "c" specifies the memory address or bus address at which the activity can be accessed. To access a particular depict or, the name of an activity is sent over bus 24 to array 25; that name is compared with part 'lo" of the depictors until a match occurs; and parts "b" and "c" of the matching depict or are sent to computer 10.
In Figure 1, part "a" of depict or 25-1 shows that it is a depict or for activity Ax; part "b" shows that activity Ax is implemented by HULL instructions in memory 11 as a procedure; and part "c" shows that the instructions begin at address 5000. Similarly, depict or 25 2 shows that activity A
is implemented by low level language instructions which begin at microcode address 200; and depict or 25-3 shows that activity A is implemented by a hardware logic unit which is at I/O bus address 100.
Reference should now be made to Figure 2 which illustrates a flow chart for the portion aye of the microcode programs 15 which is executed when a CALL instruction in program 13 is encountered. To bin as indicated by box 30, the microcode aye directs computer I to fetch the depict or that is linked to the called activity from depict or array 25.
Thereafter, as indicated by boxes 31, 32, and 33, the microcode aye directs computer 10 to examine field "b" of the fetched depict or to sense Howe the called activity is linked to an implementation mechanism.
, , , If the called activity is implemented by high level language instructions in memory 11, then the microcode aye directs computer 10 to save the present program counter and load the memory address of the called activity into the program counter. This address is contained in portion "c" of the depict or of the called activity. thereafter, the high level language instructions of the called activity are executed until the activity goes to completion; whereupon control is returned back to the calling program by reloading the program counter with the previously stored address. All of this is indicated in the flow chart at aye and 34b.
By comparison, if the called activity is implemented by a hardware logic unit, then the microcode lea directs computer 10 to send the parameters of the CALL instruction to the hardware logic unit which implements the called activity.
Thus when activity A is called, processor 10 sends parameters ml n, and o to the unit 25 at address 100 on the I/O bus 26.
Thereafter, computer 10 waits for the hardware unit to return the results of the operations that it performs. This is indicated in the flow chart at aye and 35b.
Finally, if the microcode aye detects that the called activity is performed by a special purpose microcode prowar, then the present microcode address counter is saved and the beginning address of the called activity in microcode memory 16 is loaded into the microcode address register. Thereafter, microcode in the called activity is executed until the called activity goes to completion; whereupon the saved microcode address is reloaded back into the microcode address register.
This is indicated in the flow chart at aye and 36b.
One preferred architecture for the logic circuitry in computer 10 which is adapted to achieve the above steps is illustrated in Figure 3. That architecture includes a HULL bus interface 12, a LULL bus interface 23, and an I/O bus interface I
26 which respectively correspond to the buses which were previously described in conjunction with Figure 1.
A program counter register 40 is provided for addressing HULL
instructions on bus 12; and an instruction register 41 is provided or receiving HULL instructions from bus 12. Also, a stack 42 is provided for saving the present contents of the program counter 40 and for reloading those saved contents back into the prowar counter.
A microcode address register 43 is provided in the Figure 3 architecture for addressing LULL instructions on bus 23; and a microcode instruction register 44 is provided for receiving LULL instructions from bus 23. Also, another stack 45 is provided for saving the present content of microcode address register 43 and for restoring addresses back into the microcode address register 43.
An I/O bus address register 46 is provided in the Figure architecture on bus 26 to transmit addresses on the bus and thereby select one of the units that are to the bus.
Also, an I/O bus data register 47 is provided for sending parameters to the selected unit and for receiving data therefrom.
One feature of the above-described system of Figures 1 3 is its versatility. To have the option of implementing an activity via a high level language procedure, a low level language microcode program, or a hardware logic unit is very desirable since various speed-cost tradeoffs can thereby be made.
If high speed is the primary design goal of the system then the frequently used activities should be implemented by a microcode or hardware logic units. this is because microcode and logic circuits can perform more primitive operations than high level language instructions.
Thus, they can be arranged to perform a given task more efficiently. Also, microcode and logic circuitry operates more quickly than HULL instructions.
On the other hand, if low cost is the primary design goal, then most of the activities should be implemented by high level language procedures. This is because top cost of relatively slow HULL memory space is less khans the cost of relatively fast LULL microcode memory space or high speed logic circuitry.
Another feature of the above described system is that the means by which a particular activity is implemented is very easy to change with time. For example, an activity that had previously been implemented by a high level language procedure can be implemented at a later date as a low level language program or a hardware logic unit.
Such a change is achieved by merely providing the low level language program or hardware logic unit along with a new depict or in depict or array 25. By this means, the speed of a particular system can be enhanced from time to time without changing the system's overall architecture.
The present invention may be incorporated into a multiprocessor system to improve that system's versatility and performance.
Figure 4 of the resent case illustrates such a multi-processor system with modifications that incorporate the present invention. This Figure 4 system includes a pair of digital pro-censors Pi and Pi which are coupled together via bus 50. Processor Pi is also coupled to a memory 51 via a high level language bus 52;
and processor Pi is coupled to a memory 53 via a high level language bus 54.
Jo Included in memory 51 is a program 55 which contains a sequence of high level language instructions 56. One of those instructions aye is a CALL instruction which calls an activity AX pi that processor Pi performs; while another of those instructions 56b is a CALL instruction which calls an activity Apogee that processor Pi performs.
In operation, processor Pi executes the instructions 56 until it encounters one of the CALL instructions aye or 56b. When that occurs, processor Pi interrogates an ACTIVITY
RECORD 60 for the activity that is being called. That ACTIVITY RECORD is in a shared memory SUM; and it is accessed via bus 50 through an intelligent memory controller IMP.
Some of the entries in each ACTIVITY RECORD 60 are illustrated in Figure 4. They include various FLAGS, a CALLER
entry, an ACTIVITY QUEUE HEAD (ASH) entry, a NEXT IN QUEUE
(NIX) entry, and an ACTIVITY QUEUE TAIL (AT) entry.
If the flags indicate that the called activity is DORMANT, then a pointer to the calling program (i.e., program 55~ is placed in the caller entry; whereas if the flags indicate that the activity is ACTIVE, then a pointer to the galling activity is placed in the activity's queue.
Later, when processor Pi completes the execution of the activity that it was performing, it interrogates the PROCESSOR RECORDS and ACTIVITY RECORDS to determine which activity to execute next. Actions then occur to determine which activity processor Pi performs next.
Now, in accordance with the present invention, each activity record also includes an activity depict or 61.
Physically, each depict or 61 is a rewritten thirty-two bit word in a random access memory or a thirty-two bit resister in a register array. And after processor Pi selects an activity to perform, it then examines depict or 61 of the selected activity to determine how the activity is implemented and how it can be accessed Preferably, depict or 61 contains a portion "b" which indicates whether the corresponding activity is implemented via a high level language program, a low level language microcode program, or a hardware logic unit. Also preferably, depict or 61 contains a portion "c" which indicates how that activity can be accessed.
During its examination of depict or 61, processor P
performs all of the previously described steps of Figure 2.
Thus it examines portion "b" to determine whether the selected activity is implemented by a software program 71, a firmware program 72, or a hardware logic unit 73. Lien it utilizes the information in portion "c" to activate the activity as indicated at Ahab.
In like manner, when processor Pi calls an activity which it performs, the processor then examines the depict or for that activity to determine whether it is implemented by a software program 74, a microcode program 75, or a hardware logic unit 76. Then, depending on that determination, it performs steps Ahab, Ahab, or Ahab of Figure 2. -Thus, the multiprocessor system of Figure 4 has both the versatility and changeability features of the single processor system of Figure 1. If high speed is the primary design goal of the Figure 4 system, then the frequently used activities should be implemented by low level language microcode programs or hardware logic units. And the performance of the multiprocessor system can be enhanced with time by substituting low level language programs or hardware 3$
logic units for various activities that previously had been implemented by high level language software programs, and by providing new activity depictors 61 in the activity's record 60 to reflect this change.
Various preferred embodiments of the invention have now been described in detail. In addition, however, many changes and modifications can be made to these details without departing from the nature and spirit of the invention.
Accordingly, the invention is not -to be limited to said details but is defined by the appended claims.
VIA DEPIC.OR-LINKED MICROCODE AND LOGIC CIRCUITRY
BACKGROUND OF THE INVENTION
This invention relates to data processing systems;
and in particular, it relates to methods of operating such systems.
Conventionally, a data processing system is operated by providing a program which consists of a sequence of instructions of some predetermined language These instructions are executed one at a time; and the particular instruction that is currently being executed is pointed to by a program counter.
Each time the execution of an instruction it completed, the program counter is incremented to point Jo the next sequential instruction unless the completed instruction was a UP instruction or a CALL instruction. When a JUMP
instruction is encountered, the program counter is loaded with a new address as the JUMP instruction directs; and then :
instructions are sequentially executed beginning at that Noah address. By comparison, when a CALL instruction is encountered, an independent procedure is executed and then control passes back to the instruction which follows the CALL
instruction.
A procedure is a separate special purpose sequence of instruction-from the same predetermined language of which the program that called it is made up. From the point of view of the calling program, a procedure can be regarded as a single new higher level instruction even though it may be quite complicated and made up of hundreds of instructions from the predetermined language.
By writing a collection of procedures, a programmer can define a new level instruction set. Then programs in the predetermined language can be written which use this new level instruction set by referring to them through the CALL
instruction. Additional details on this prior art method of structuring or partitioning a program are found in the Prentice-Hall textbook entitled Structured Computer Or~lzation by Andrew S. Tanenbaum, 1976, at pages 120-130.
One problem, however, with having a data processing system operate to execute a program which includes several CALL instructions and their corresponding procedures is that the system operates too slowly. This fact and the manner in which the execution speed can be greatly enhanced in accordance with the present invention is explained in detail in the following Detailed Description.
Still another problem with the prior art method of operating a data processing system by means of CALL
instructions and corresponding procedures is that the operation is too inflexible. In particular, the operation is too confined to include special purpose microcode routines or special purpose hardware logic units that perform procedure-like functions.
I
BRIEF SUMMARY OF THE INVASION
Accordingly, a primary object of the invention is to provide an improved method of operating a data processing system.
Another object of the invention is to provide a method of enhancing the speed at which a data processing system operates.
Still another object of the invention is to provide a method of operating a data processing system wherein procedure e functions are performed by low level language microcode routines and hardware logic units.
In the present invention, the above objects and others are achieved by operating a data processing system in a manner which includes the steps of:
storing, in a memory, a software program that contains first and second instructions which respectively call for first and second activities;
linking the first instruction via one type of depict or to a software procedure that performs the first activity, while linking the second instruction via a different type of depict or to a non-software mechanism that performs the second activity;
executing the software program until either the first or second instruction is encountered;
sensing whether the encountered instruction is linked to its activity by the one type or the different type depict or; and executing the procedure if the sensing step dejects the one type depict or; but activating the non-software mechanism if the sensing step detects the different type depict or.
Preferably, the activating step of the non-software mechanism can include the sub step of executing a microcode program to perform the second activity; or alternatively, it includes the sub step of sending parameters to a hardware logic unit to perform the second activity. Also preferably, the depict or in the above-recited method is a partitioned register in winch one portion contains the name of the activity that is to be performed; another portion indicates whether the named activity is implemented via a procedure, a microcode routine, or a hardware logic unit; and another portion indicates how the named activity can be accessed.
BRIEF DESCRIPTION OF THE DRUNKS
Various features and advantages of the invention are described in the following Detailed Description in conjunction with the accompanying drawings wherein:
Figure 1 illustrates one embodiment of a data processing system that is constructed according to the invention;
Figure 2 illustrates the steps that are there taken by the Figure 1 system when a CALM, instruction is executed;
Figure 3 illustrates the details of the hardware components in the computer of the Figure 1 system that are affected by the steps of Figure 2;
Figure 4 illustrates another embodiment of a data processing system that is constructed according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to Figure 1, a data processing system and method of operating the system in accordance with the invention will be described. Included in the Figure 1 system is a digital computer 10 which is coupled to a memory 11 via a bus 12. A software program 13 which computer 10 executes is stored in memory 11.
As used herein, the term "software program" means a sequence of high level language (HULL) instructions with each such instruction being interpreted by a microcode program of low level language (LULL) instructions In turn, the low level language instructions are executed directly by digital logic circuitry in computer 10. Individual high level language instructions in software program 13 are indicated by reference numeral 14; and the low level language microcode programs are indicated by reference numeral 15 in a memory 16.
Three of the illustrated high level language instructions 14 are CALL instructions lea, 14b, and 14c which have been modified to operate in accordance with the present invention. This modified CALL instruction identifies an activity by name, discontinues the execution of the HULL
software program of which it is a part, saves sufficient information to resume execution of the discontinued program at a later time at the point of discontinuance, and initiates the execution of the named activity by passing parameters and control to it.
For example, CALL instruction aye identifies an activity Ax to which control is to be passe along with parameters j and k. Similarly, CALL instruction 14b identifies an activity A to which control is to be passed along with a parameter I And CALL instruction 14c identifies another activity A to which control is to be passed along with parameters m, n, and o.
Each of the activities Ax, Aye and A is either a special purpose software program (ire., a procedure), a special purpose microcode program, or a special purpose hardware logic unit. In each case, the activity is adapted to receive parameters from the CALL instruction, operate on the received parameters in a predetermined fashion, and indicate to the CALL instruction that the operation is complete. For example, one activity may receive the names of several records as parameters from the CALL instruction, -read the identified records from various storage units, and sort them in a predetermined order.
In Figure 1, activity Ax is indicated by reference numeral 20 as being a special purpose procedure of HULL
instructions in memory 11. Those high level language instructions are frown the same language as the instructions which make up program 13. To execute activity Ax the address of the beginning high level language instruction in activity Ax is loaded into a program counter in computer 10; and then instructions from activity Ax are read via the high level language bus 12 into computer 10 where they are interpreted by the microcode programs 15.
By comparison, activity A is indicated by reference numeral 21 in Figure 1 as being a special purpose microcode program in memory 16. Microcode program 21 is made up of a sequence of low level language instructions which are read over a low level language bus 22 into computer 10 where they are executed directly by the computer's digital logic circuitry.
Also as is indicated by reference numeral 23, activity A is comprised of a special purpose logic unit which is coupled via an I/O bus 24 to computer 10. When a CALL
instruction in program 13 is encountered which calls activity A, computer 10 sends the parameters of the CALL instruction to unit 23 via bus 24 and then merely waits for unit 23 to return the results of the operation which the activity performs.
A depict or array 25 is also coupled to the I/O bus 24; and it contains respective depictors for each activity that is called in program 13. thus the Figure 1 array contains three depictors 25-1, 25-2~ and 25-3. By a depict or is herein meant a mechanism which links a named activity to other information which describes how the named activity can be accessed.
In one preferred embodiment, each depict or in array 27 is a content addressable hardware register that is partitioned into three parts, "a", "b". and "c". Part "a"
contains the nave of the activity. Part "b" identifies whether the named activity is a software program in memory 11 or a microcode program in memory 16 or a hardware logic unit on I/O bus 24. And part "c" specifies the memory address or bus address at which the activity can be accessed. To access a particular depict or, the name of an activity is sent over bus 24 to array 25; that name is compared with part 'lo" of the depictors until a match occurs; and parts "b" and "c" of the matching depict or are sent to computer 10.
In Figure 1, part "a" of depict or 25-1 shows that it is a depict or for activity Ax; part "b" shows that activity Ax is implemented by HULL instructions in memory 11 as a procedure; and part "c" shows that the instructions begin at address 5000. Similarly, depict or 25 2 shows that activity A
is implemented by low level language instructions which begin at microcode address 200; and depict or 25-3 shows that activity A is implemented by a hardware logic unit which is at I/O bus address 100.
Reference should now be made to Figure 2 which illustrates a flow chart for the portion aye of the microcode programs 15 which is executed when a CALL instruction in program 13 is encountered. To bin as indicated by box 30, the microcode aye directs computer I to fetch the depict or that is linked to the called activity from depict or array 25.
Thereafter, as indicated by boxes 31, 32, and 33, the microcode aye directs computer 10 to examine field "b" of the fetched depict or to sense Howe the called activity is linked to an implementation mechanism.
, , , If the called activity is implemented by high level language instructions in memory 11, then the microcode aye directs computer 10 to save the present program counter and load the memory address of the called activity into the program counter. This address is contained in portion "c" of the depict or of the called activity. thereafter, the high level language instructions of the called activity are executed until the activity goes to completion; whereupon control is returned back to the calling program by reloading the program counter with the previously stored address. All of this is indicated in the flow chart at aye and 34b.
By comparison, if the called activity is implemented by a hardware logic unit, then the microcode lea directs computer 10 to send the parameters of the CALL instruction to the hardware logic unit which implements the called activity.
Thus when activity A is called, processor 10 sends parameters ml n, and o to the unit 25 at address 100 on the I/O bus 26.
Thereafter, computer 10 waits for the hardware unit to return the results of the operations that it performs. This is indicated in the flow chart at aye and 35b.
Finally, if the microcode aye detects that the called activity is performed by a special purpose microcode prowar, then the present microcode address counter is saved and the beginning address of the called activity in microcode memory 16 is loaded into the microcode address register. Thereafter, microcode in the called activity is executed until the called activity goes to completion; whereupon the saved microcode address is reloaded back into the microcode address register.
This is indicated in the flow chart at aye and 36b.
One preferred architecture for the logic circuitry in computer 10 which is adapted to achieve the above steps is illustrated in Figure 3. That architecture includes a HULL bus interface 12, a LULL bus interface 23, and an I/O bus interface I
26 which respectively correspond to the buses which were previously described in conjunction with Figure 1.
A program counter register 40 is provided for addressing HULL
instructions on bus 12; and an instruction register 41 is provided or receiving HULL instructions from bus 12. Also, a stack 42 is provided for saving the present contents of the program counter 40 and for reloading those saved contents back into the prowar counter.
A microcode address register 43 is provided in the Figure 3 architecture for addressing LULL instructions on bus 23; and a microcode instruction register 44 is provided for receiving LULL instructions from bus 23. Also, another stack 45 is provided for saving the present content of microcode address register 43 and for restoring addresses back into the microcode address register 43.
An I/O bus address register 46 is provided in the Figure architecture on bus 26 to transmit addresses on the bus and thereby select one of the units that are to the bus.
Also, an I/O bus data register 47 is provided for sending parameters to the selected unit and for receiving data therefrom.
One feature of the above-described system of Figures 1 3 is its versatility. To have the option of implementing an activity via a high level language procedure, a low level language microcode program, or a hardware logic unit is very desirable since various speed-cost tradeoffs can thereby be made.
If high speed is the primary design goal of the system then the frequently used activities should be implemented by a microcode or hardware logic units. this is because microcode and logic circuits can perform more primitive operations than high level language instructions.
Thus, they can be arranged to perform a given task more efficiently. Also, microcode and logic circuitry operates more quickly than HULL instructions.
On the other hand, if low cost is the primary design goal, then most of the activities should be implemented by high level language procedures. This is because top cost of relatively slow HULL memory space is less khans the cost of relatively fast LULL microcode memory space or high speed logic circuitry.
Another feature of the above described system is that the means by which a particular activity is implemented is very easy to change with time. For example, an activity that had previously been implemented by a high level language procedure can be implemented at a later date as a low level language program or a hardware logic unit.
Such a change is achieved by merely providing the low level language program or hardware logic unit along with a new depict or in depict or array 25. By this means, the speed of a particular system can be enhanced from time to time without changing the system's overall architecture.
The present invention may be incorporated into a multiprocessor system to improve that system's versatility and performance.
Figure 4 of the resent case illustrates such a multi-processor system with modifications that incorporate the present invention. This Figure 4 system includes a pair of digital pro-censors Pi and Pi which are coupled together via bus 50. Processor Pi is also coupled to a memory 51 via a high level language bus 52;
and processor Pi is coupled to a memory 53 via a high level language bus 54.
Jo Included in memory 51 is a program 55 which contains a sequence of high level language instructions 56. One of those instructions aye is a CALL instruction which calls an activity AX pi that processor Pi performs; while another of those instructions 56b is a CALL instruction which calls an activity Apogee that processor Pi performs.
In operation, processor Pi executes the instructions 56 until it encounters one of the CALL instructions aye or 56b. When that occurs, processor Pi interrogates an ACTIVITY
RECORD 60 for the activity that is being called. That ACTIVITY RECORD is in a shared memory SUM; and it is accessed via bus 50 through an intelligent memory controller IMP.
Some of the entries in each ACTIVITY RECORD 60 are illustrated in Figure 4. They include various FLAGS, a CALLER
entry, an ACTIVITY QUEUE HEAD (ASH) entry, a NEXT IN QUEUE
(NIX) entry, and an ACTIVITY QUEUE TAIL (AT) entry.
If the flags indicate that the called activity is DORMANT, then a pointer to the calling program (i.e., program 55~ is placed in the caller entry; whereas if the flags indicate that the activity is ACTIVE, then a pointer to the galling activity is placed in the activity's queue.
Later, when processor Pi completes the execution of the activity that it was performing, it interrogates the PROCESSOR RECORDS and ACTIVITY RECORDS to determine which activity to execute next. Actions then occur to determine which activity processor Pi performs next.
Now, in accordance with the present invention, each activity record also includes an activity depict or 61.
Physically, each depict or 61 is a rewritten thirty-two bit word in a random access memory or a thirty-two bit resister in a register array. And after processor Pi selects an activity to perform, it then examines depict or 61 of the selected activity to determine how the activity is implemented and how it can be accessed Preferably, depict or 61 contains a portion "b" which indicates whether the corresponding activity is implemented via a high level language program, a low level language microcode program, or a hardware logic unit. Also preferably, depict or 61 contains a portion "c" which indicates how that activity can be accessed.
During its examination of depict or 61, processor P
performs all of the previously described steps of Figure 2.
Thus it examines portion "b" to determine whether the selected activity is implemented by a software program 71, a firmware program 72, or a hardware logic unit 73. Lien it utilizes the information in portion "c" to activate the activity as indicated at Ahab.
In like manner, when processor Pi calls an activity which it performs, the processor then examines the depict or for that activity to determine whether it is implemented by a software program 74, a microcode program 75, or a hardware logic unit 76. Then, depending on that determination, it performs steps Ahab, Ahab, or Ahab of Figure 2. -Thus, the multiprocessor system of Figure 4 has both the versatility and changeability features of the single processor system of Figure 1. If high speed is the primary design goal of the Figure 4 system, then the frequently used activities should be implemented by low level language microcode programs or hardware logic units. And the performance of the multiprocessor system can be enhanced with time by substituting low level language programs or hardware 3$
logic units for various activities that previously had been implemented by high level language software programs, and by providing new activity depictors 61 in the activity's record 60 to reflect this change.
Various preferred embodiments of the invention have now been described in detail. In addition, however, many changes and modifications can be made to these details without departing from the nature and spirit of the invention.
Accordingly, the invention is not -to be limited to said details but is defined by the appended claims.
Claims (11)
1. A method of operating a data processing system including the steps of:
storing, in a memory means, one software program that contains first and second instructions which respectively call first and second activities;
linking said first instruction via one type of depictor to another software program that performs said first activity, and linking said second instruction via a different type of depictor to a non-software means that performs said second activity;
executing said one software program until either said first or second instruction is encountered;
sensing whether said encountered instruction is linked to its activity by said one type or said different type depictor; and executing said another software program if said sensing step detects said one type depictor; and activating said non-software means if said sensing step detects said different type depictor.
storing, in a memory means, one software program that contains first and second instructions which respectively call first and second activities;
linking said first instruction via one type of depictor to another software program that performs said first activity, and linking said second instruction via a different type of depictor to a non-software means that performs said second activity;
executing said one software program until either said first or second instruction is encountered;
sensing whether said encountered instruction is linked to its activity by said one type or said different type depictor; and executing said another software program if said sensing step detects said one type depictor; and activating said non-software means if said sensing step detects said different type depictor.
2. A method according to Claim 1 wherein said activating step includes the substep of executing a microcode program in response to the sensing of said different type depictor to perform the activity called by said encountered instruction.
3. A method according to Claim 1 wherein said activating step includes the substep of sending parameters to a hardware logic means in response to the sensing of said different type depictor to perform the activity called by said encountered instruction.
4. A method according to Claim 1 wherein said linking step includes the substep of writing an address of said another software program into said one type depictor and writing an address of a microcode program into said different type depictor.
5. A method according to Claim 1 wherein said linking step includes the substep of writing an address of said another software program into said one type depictor and writing an address of a hardware logic means into said different type depictor.
6, A method of operating a data processing system including the steps of:
executing one software program until an instruction is encountered which calls an activity;
sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor;
executing another software program for performing the called activity if said sensing step detects said first type depictor; and activating a non-software means for performing said called activity if said sensing step detects said second type depictor.
executing one software program until an instruction is encountered which calls an activity;
sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor;
executing another software program for performing the called activity if said sensing step detects said first type depictor; and activating a non-software means for performing said called activity if said sensing step detects said second type depictor.
7. A method according to Claim 6 wherein said activating step includes the substep of executing a microcode program in response to the sensing of said second type depictor to perform the activity called by said encountered instruction.
8. A method according to Claim 6 wherein said activating step includes the substep of sending parameters to a hardware logic means in response to the sensing of said second type depictor to perform the activity called by said encountered instruction.
9. A method according to Claim 6 wherein said sensing step is performed by executing a set of microcode commands.
10. A method according to Claim 6 and further including the step of repeating all of the steps of Claim 6 until the execution of said one software program is complete.
11. A data processing system comprising:
a memory means containing a software program for a computer means to execute;
said program including first and second instructions which respectively all first and second activities to perform predetermined tasks;
first and second depict or means which respectively correspond to said first and second activities;
said first depict or means including a first code and a pointer to another software program for performing said first activity; and said second depict or means including a second code and a pointer to a non-software means for performing said second activity.
a memory means containing a software program for a computer means to execute;
said program including first and second instructions which respectively all first and second activities to perform predetermined tasks;
first and second depict or means which respectively correspond to said first and second activities;
said first depict or means including a first code and a pointer to another software program for performing said first activity; and said second depict or means including a second code and a pointer to a non-software means for performing said second activity.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/528,461 US4862351A (en) | 1983-09-01 | 1983-09-01 | Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same |
| US528,461 | 1983-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1214565A true CA1214565A (en) | 1986-11-25 |
Family
ID=24105774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000462175A Expired CA1214565A (en) | 1983-09-01 | 1984-08-30 | Method of operating a data processing system via depictor-linked microcode and logic circuitry |
Country Status (5)
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|---|---|
| US (1) | US4862351A (en) |
| EP (1) | EP0138352B1 (en) |
| CA (1) | CA1214565A (en) |
| DE (1) | DE3484725D1 (en) |
| WO (1) | WO1985001136A1 (en) |
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|---|---|---|---|---|
| DE3750311T2 (en) * | 1986-05-30 | 1995-03-30 | Bull Hn Information Syst | Device and method for transfer between processors. |
| JPS63278145A (en) * | 1987-05-11 | 1988-11-15 | Nec Corp | Parameter correspondence check system |
| US4961133A (en) * | 1987-11-06 | 1990-10-02 | Visystems, Inc. | Method for providing a virtual execution environment on a target computer using a virtual software machine |
| AU4414889A (en) * | 1988-10-21 | 1990-05-14 | A.C. Nielsen Company | Software operating environment |
| JPH02190930A (en) * | 1988-12-29 | 1990-07-26 | Internatl Business Mach Corp <Ibm> | Software instruction executing apparatus |
| US5146593A (en) * | 1989-03-06 | 1992-09-08 | International Business Machines Corporation | Procedure call interface |
| US5068821A (en) * | 1989-03-27 | 1991-11-26 | Ge Fanuc Automation North America, Inc. | Bit processor with powers flow register switches control a function block processor for execution of the current command |
| GB2232514B (en) * | 1989-04-24 | 1993-09-01 | Yokogawa Electric Corp | Programmable controller |
| DE69029441T2 (en) * | 1989-08-24 | 1997-06-12 | Ibm | System for calling procedures from a remote network node |
| US5218699A (en) * | 1989-08-24 | 1993-06-08 | International Business Machines Corporation | Remote procedure calls in heterogeneous systems |
| GB2242293A (en) * | 1990-01-05 | 1991-09-25 | Apple Computer | Apparatus and method for dynamic linking of computer software components |
| JPH0831041B2 (en) * | 1991-09-06 | 1996-03-27 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Program condition processing method and computer system |
| US5319784A (en) * | 1991-12-18 | 1994-06-07 | International Business Machines Corp. | System for automatic and selective compile-time installation of fastpath into program for calculation of function/procedure without executing the function/procedure |
| US5409200A (en) * | 1992-03-05 | 1995-04-25 | Zingher; Arthur R. | Printed-circuit-like array of springs with non-linear force vs deflection |
| US5504920A (en) * | 1994-05-16 | 1996-04-02 | Compaq Computer Corporation | Video driver system for communicating device specific primitive commands to multiple video controller types |
| US6542854B2 (en) * | 1999-04-30 | 2003-04-01 | Oracle Corporation | Method and mechanism for profiling a system |
| GB2412192B (en) * | 2004-03-18 | 2007-08-29 | Advanced Risc Mach Ltd | Function calling mechanism |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3478322A (en) * | 1967-05-23 | 1969-11-11 | Ibm | Data processor employing electronically changeable control storage |
| US3983539A (en) * | 1969-05-19 | 1976-09-28 | Burroughs Corporation | Polymorphic programmable units employing plural levels of sub-instruction sets |
| US3614745A (en) * | 1969-09-15 | 1971-10-19 | Ibm | Apparatus and method in a multiple operand stream computing system for identifying the specification of multitasks situations and controlling the execution thereof |
| US3631405A (en) * | 1969-11-12 | 1971-12-28 | Honeywell Inc | Sharing of microprograms between processors |
| BE758813A (en) * | 1969-11-28 | 1971-04-16 | Burroughs Corp | PROGRAM STRUCTURES FOR THE IMPLEMENTATION OF INFORMATION PROCESSING SYSTEMS COMMON TO HIGHER LEVEL PROGRAM LANGUAGES |
| US3735363A (en) * | 1971-04-07 | 1973-05-22 | Burroughs Corp | Information processing system employing stored microprogrammed processors and access free field memories |
| BE795789A (en) * | 1972-03-08 | 1973-06-18 | Burroughs Corp | MICROPROGRAM CONTAINING A MICRO-RECOVERY INSTRUCTION |
| US4131941A (en) * | 1977-08-10 | 1978-12-26 | Itek Corporation | Linked microprogrammed plural processor system |
| US4149243A (en) * | 1977-10-20 | 1979-04-10 | International Business Machines Corporation | Distributed control architecture with post and wait logic |
| JPS54104251A (en) * | 1978-02-02 | 1979-08-16 | Toshiba Corp | Data processor |
| US4257096A (en) * | 1978-10-23 | 1981-03-17 | International Business Machines Corporation | Synchronous and conditional inter-program control apparatus for a computer system |
| US4325121A (en) * | 1978-11-17 | 1982-04-13 | Motorola, Inc. | Two-level control store for microprogrammed data processor |
| US4253145A (en) * | 1978-12-26 | 1981-02-24 | Honeywell Information Systems Inc. | Hardware virtualizer for supporting recursive virtual computer systems on a host computer system |
| US4454579A (en) * | 1981-09-11 | 1984-06-12 | Data General Corporation | System for performing call and return operations |
| US4454580A (en) * | 1981-09-16 | 1984-06-12 | International Business Machines Corporation | Program call method and call instruction execution apparatus |
| US4484272A (en) * | 1982-07-14 | 1984-11-20 | Burroughs Corporation | Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion |
| US4463423A (en) * | 1982-07-14 | 1984-07-31 | Burroughs Corporation | Method of transforming high level language statements into multiple lower level language instruction sets |
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1983
- 1983-09-01 US US06/528,461 patent/US4862351A/en not_active Expired - Lifetime
-
1984
- 1984-08-30 CA CA000462175A patent/CA1214565A/en not_active Expired
- 1984-08-30 WO PCT/US1984/001387 patent/WO1985001136A1/en unknown
- 1984-08-31 EP EP84305968A patent/EP0138352B1/en not_active Expired - Lifetime
- 1984-08-31 DE DE8484305968T patent/DE3484725D1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE3484725D1 (en) | 1991-07-25 |
| US4862351A (en) | 1989-08-29 |
| EP0138352B1 (en) | 1991-06-19 |
| EP0138352A2 (en) | 1985-04-24 |
| EP0138352A3 (en) | 1988-03-16 |
| WO1985001136A1 (en) | 1985-03-14 |
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