CA1321035C - Apparatus and method for alterable resource partitioning enforcement in a data processing system having central processing units using different operating systems - Google Patents

Abstract

ABSTRACT
In a data processing system having a plurality of non-homogeneous central processing units, apparatus is disclosed that permits a central processing unit not having mechanisms for protection of the allocation of resources to be coupled to the data processing system while preserving a peer relationship among the central processing units. The protection apparatus is interposed between the coupled central processing unit and the system bus and reviews each access to data processing system resources to insure that the accessed system resource is available to the associated data processing system. In addition, the apparatus permits initialization procedures without interprocessor conflict, provides status information from the coupled central processing unit to a requesting central processing unit and permits selected control signals to be applied to the coupled central processing unit.

Description

132103~
1 ~2434-90 APPARATUS AND METHOD FOR ALTERABLE RESOU~CE
PARTITIONING ENFORCEMENT IN A DATA PROCESSING
SYSTEM HAVING CENTRAL PROCESSING UNITS
USING DIFFERENT OPERATING SYSTEMS

RELATED APPLICATIONS
The following Canadian Patent Applications are related applications to the present invention A PEER RELATIONSHIP AMONG A PLURALITY OF CENTRAL PROCESSING UNITS;
invented by John L. Curley, Thomas S. Hirsch, John C. Penney, Ileana S. Reisch; Theodore R. Staplin, Jr., and David A. Wurz;
having Serial No. 585,057; filed on December 6, 1988 and assigned to the assignee of the present Canadian Patent Application.
APPARATUS AND METHOD FOR ACCESS TO USER PROGRAMS
- CONTROELED BY A FIRST OPERATING SYSTEM BY USERS INTERACTING WITH A
DATA PROCESSING SYSTEM THROUGH A SECOND OPERATING SYSTEM; invented by John L. Curley, Thomas S. Hirsch, John C. Penney, Ileana S.
Reisch; James M. Sandini, Theodore R. Staplin, Jr., and David A.
Wurz; having Serial No. 586,380; filed on December 20, 1988 and asslgned to the assignee of the present Canadian ~ . .

i32~3~

Patent Application.
BACKGROUND OF THE INVENTION
1. Fiel~Lof~-t~hl~e-lnvention This invention relates generally to data processing systems and more particularly to data processing systems having a plurality of central processing units.

2. Description of the Related Art In order to increase the processing capability of data processing systems, one technique has been to couple additional central processing units to the system. The ability to select the number of central processing units in a data processing system permits an efficient matching of the capabilities of the system to the data processing requirements. Data processing units having a plurality of central processing units typically have one of two configurations. Referring now to Fig. lA, a data processing system having a plurality of central processing units, according to a first implementation found in the prior art, is shown. The data processing system includes a plurality of central processing units 11-12 coupled to a system bus 19.
The central processing units 11-12 perform the actual manipulation of data groups under control of operating and user software programs. The main memory unit 16, also coupled to the system bus 19, , ~.~. "
;

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stores the data and program signal groups which are currently being used by the central processing units.
The input~output units 14-15, coupled to the system bus 19, include devices for storage of large S quantities of data and program signal groups, e.g., disk storage devices, terminals for the entry of data by system users, and communication devices for exchange of data and program groups with remote locations. The system bus 19 provides the principal lo path for the exchange of data and program groups between ths components of the data processing system.
Referring next to Fig. lB, a second implementation of a multiprocessor system, according to the related art, i5 shown. Generally, the same components are available to perform the processing functions as in Fig. lA except that the components are coupled by a memory control unit 14 instead of by the system bus 19. The memory control unit 14 is typically an electronic switch providing the coupling of the data processing unit component in response to control signals. The memory control unit 14 can also provide functionality, such as conflict resolution, that would typically be distributed in the bus oriented data processing system.
The data processing systems of Fig. lA and Fig.
lB are typically implemented in the related art such that the central processing units are homogeneous. In 132103~

a homogeneous data processing system, the operating systems are the same or similar, the implementing apparatus is the same or similar and the operations performed on apparatus external to the data processing system is the same or similar. Even though the central processing units are homogeneous, substantial efforts are employed to prevent conflicts between the central processing units, thereby preventing conflicts between different activities for lo the data processing system resources. For example, one of the central processing systems can be selected to allocate resources and tasks among the plurality of central processing units. The resources of the system are the storage devices, terminals, main memory locations and other data processing facilities to which a central processing unit has access for the purpose of performing the data processing functions.
This relationship is generally referred to as the master/slave relationship because of the control asserted by the selected processor. However, some data processing systems can be designed wherein the central processing units, operating under cont~ol of the same operating system, can operate under as equal members (a5 contrasted with the master/slave relationship) of the data processing system. The following references provide examples of the way in which a plurality of central processing units can be 1 3 2 ~ Q 3 ~

incorporated in a data processing system without a master/slave relationship while avoiding system resource access conflicts.
In U.S. Patent 3,6~1,405, issued December 28, 1971, entitled SHARING OF MICROPROGRAMS BETWEEN
PROCESSORS and invented by G. S. Hoff and R. P.
Kelly, two microprogrammed processing units share control elements that permit sharing of microprogram repertoires. By appropriate invocation of the lo operating system, the control signals from a first microprogrammed processing unit are transferred to the second microprogrammed processing unit. In fact~
this configuration can best be described as a single processing unit with resources allocated by a supervisor controlled operating system. The use of a supervisor program as well as the coupling between the two processing units distinguishes this configuration from the peer processing unit relationship described in the present invention.
In U.S. Patent 4,131,941, issued December 26, 1978, entitled LINKED MICROPROGRAMMED PLURAL
PROCESSOR UNIT and invented by H. L. Siegel, G. F.
Muething, Jr., and E. J. Radkowski, a configuration o~ a plurality of processors is described that permits the processors to act independently or to be reconfigured so that a master/slave relationship can be invoked. The plurality of processors are linked 1 3 ~
-6- ~
together and, even when operating in a mode described as being independent, are n~t independent but subject to a supervisory control structure for con~guration determination and for allocation of activity. Of course, the control of the allocati~n o~ activities implies the control of the allocation of resources.
In addition, the data processing system described by this U.S. Patent, either has one operating system or a plurality of identical operating systems. The invention of the U.S. Patent appears to be best described as a single data processing system with a controllable configuration. The present invention is directed to central processing llnits having different operating systems that can function independently.
In U.S. Patent 4,200,930, issued on April 29, 1980, entitled ADAPTER CLUSTER MODULE FOR DATA
COMMUNICATIONS SUBSYSTEM invented by R. L. Rawlings and R. D. Mathews, a host processing unit can have a plurality data communications subsystems coupled thereto for performing routine communications functions with incoming and outgoing signals.
Although the data communications subsystems are capable, in case of a failure of the host processing unit, of continuing communications, thP role of the host processing unit to the data communications subsystems is clearly that of a master/slave relationship. The peer processor relationship is not 1321~3~

applicable because the data communications subsystems do not have access to all the resources available to the host processing unit In U.S. Patent 4,722to4a issued January 26, 1988, entltled MICROCOMPUTER SYSTEM WITH INDEPENDENT OPERATING SYSTEMS, invented by T. S. Hirsch, J. W. Stonier and T. O. Holtey, two processors, an LSI-6 processor with a MOD400 operating system and an *Intel 8086 processor with either and MS-DOS or a CPM-86 operating share the processing responsibilities (a *Motorola 6809 microprocessor is al60 included, but generally functions as an input/output controller~. The LSI-6 processor has memory space that is not accessible to the Intel 8086 processor. In addition, the input/output operations performed by the 6809 microprocessor can be initiated only by the LSI-6 processor, so that the Intel 8086 has access to this resource only through the intervention of the LSI-6 processor, a form of a master/slave relationship.
There has also been proposed a system for communication of two processors in which the sharlng of memory without interference is accomplished by controlling buses associated with each processor system. The buses are coupled to *Trade-mark , ' , , -8- ~32~03~
particular areas of memory and, for one processor to access the memory dedicated to the second processor, the bus of the first processor is coupled to the bus of the s~cond processor. Apparatus associated with each bus controls the ability of the other processor to access the system bus, thereby effectively limiting access of each processor to the system resources.
More recently, interest has been demonstrated in data processing systems having a plurality of central processing units functioning with non-homogeneous (generally incompatible) characteristics. The availability of non-homogeneous central processing units can be particularly advantageous to a system user providing the availability of a plurality of program repertoires.
,- Ideally, all of the central processing units should have a peer relationship, i.e., should be capable of accessing all resources without the benefit of auxiliary protection mechanisms described in relation to the related art and without having a master/slave relationship in which one central processing unit controls all the activity and allocation of resources. Many central processing systems do not have the necessary hardware and/or software functionality, to enforce allocation of resources.
Non-the-less, the peer relationship between central , ' 132103~
g processing units is a desirable multiprocessor relat~onship, allowing easy expandability of the processing system.
A need has been felt for technique that permits any central processing unit to be coupled to a data processing system even though necessary the mechanisms for enforcement of resource allocation are not present.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved data processinq ystem that overcomes the pro~lems of the prior art.
It is a feature of the present invention to provide an improved data processing system having a plurality of central processing units.
It is another feature of the present invention to provide an improved data processing system having a plurality of central processing units utilizing different operating systems.
It is a further feature of the present invention to provide an improved data processing system in which a plurality of central processing `units executing instructions under different operating systems can have a peer relationship.
It is more particular feature of the present invention to provide apparatus permitting two central processing units of a data processing system to 32la3~
operate in a non-hierarchical relationship while controlling the interaction between the central processing units.
It is still another feature of the present invention to permit a central processing unit to be coupled to a data processing system, in which all the central processing units have a non-hierarchical relationship, even though the central processing unit being coupled to the data processing system does not lo have the requisite resource ~llocation enforcement mechanisms.
The aforementioned and other features are accomplished, according to the present invention, by coupling a central processing unit, typically not compatible with a central processing unit(s) already coupled to a data processing system, to the data processing system. The non-compatible central processing unit is coupled to the data processing system through a central processing unit interface device. The central processing unit interface device includes resource allocation mechanisms by which a data processing system which can permit the coupled céntral processing unit(s) to have access to àll of the resources of data processing system. The central processing unit interface device dynamically controls the resources to which the coupled central processing unit can have access. The central processing unit 1321~
11 72434-9o interface device also eliminates potentlal conflicts during initlalization procedures~ provldes status slgnals relatlng to the operation of the non-homogeneous central processlng unit and applied selected control signals to the non-compatible centxal processing unlt.
In accordance with the present invention there is provided a data processlng system comprising: at least a flrst and a second central processing unit, said first and said second central processing unit operatlng under control of non-homogeneous operating systems; a plurality of da~a processing system resources, each of said resources being assigned to a selected one of said central processing units, wherein said first processing system includes an internal control means for preventing access to resources not assigned to said first data processing system; and external control means coupled between said second central processing unit and a remainder of said data processing system, said external control means to prevent access to data processing system resources not assigned to said second central processing system In accordance with the present invention there is also pro~ided the method of coupling a central processing unit to a data processing system, the central processing unit operating under control of an operating system that is incompatible with said data processing system comprising the steps of: assigning selected data processing system resources to said central proce~slng unlt; prohlbiting said central processlng unit from interacting with said data processing system when said central processing unit attempts to access resources other than said , lla ~321~t~ 72434-90 ~elected data processing sy~tem resour~es; converting signal groups applied to said data processing system format compatible with signal groups processed by said data processing system; and converting signal groups from said data processing system to a format compatible with said central processing unit.
In accordance with ~he present invention there is further provided a data processing system of the type comprising at least first and second processing units and a plurality of resources, wherein said processing uni.ts and resources are coupled to a common signal transfer device for intercommunication, and wherein different ones of said resources are uniquely assigned for exclusive access by said first or second processing units; said system characterized by: said first processing unit including as part thereof security apparatus for pxeventing access by said first processing unit to resources not assigned to said first processing unit; and interface apparatus conn~cted between said common signal transfer device and said second processing unit for preventing access by said second processing unit to resources not asRigned to said second processing unit.
These and other features of the invention will be understood upon reading of the following descriptlon along with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure lA is a block diagram of a bus oriented data proce~sing system having a plurality of central processing units according to the related art, while Fig. lB is a block diagram of a memory controller oriented data processing system having a plurality of central processing units according to ~he prior art.

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llb 72434-90 Figure 2A illustrates the apparatus for implementing a peer processor relationship in a multiprocessor data proGessing system, while Flg. 2~ illustrates the partitioning of main memory storage in a peer processor relationship.
Figure 3 is a bloGk diagram of the principal components of the protection enforcement mechanism for the partitioning of resources according to the present invention.
Figure 4 is a block diagram of the central processing unit according to one implementation of ~, ~,., 1321~3~

the preferred embodiment.
Figure 5 is a block diagram of the status and control logic unit 32 of the protection en~orcement mechanism.
5Figure 6 is a block diagram illustrating the components of the dedicated memory unit 34 shown in - Fig. 3.
Figure 7 is a block diagram of the components of the main memory unit protection device and the input output protection device.
DESCRIPTION OF THE PREFERRED EMBODIMENT
1. Detailed Description of the Fiqures Referring to Fig. 2A, the principal components that permit the central processing units of a data processing system of multiprocessor data processing system to assume a peer relationship are illustrated.
Each central processing unit 11 (through 12) has associated therewith apparatus, software procedures or a combination of apparatus and software programs that prevent the generation of addressas or attempts to access input/output devices are nominally unavailable to the central processing unit 11 ,(through 12 respectively). This apparatus is illustrated a~ address generation apparatus 111 as part of central processing unit 11 and address generation security apparatus 121 as part of central processing unit 12. The main memory unit 15 is 132103~

divided into a plurality of regions. Reqion 151 is a region reserved for the operating system controlling the operation of ce.ntral processing unit 11, while region 152 is a portion of the main memory unit reserved for the operating system controlling operation of the cPntral processing unit 12. The portion of the main memory unit denoted by region 153 is reserved for the files, tables, software procedures, etc., used by the central processing unit lo 11, while the region 154 is reserved for the files, tables, software programs used by central processing unit 12. Region 155 is a common region and accessible to both central processing unit ll and central processing unit 12.
15Referring to Fig. 2B, more detail- in the allocation of the storage of the main memory unit 15 is shown symbolically. The regions 151 and 152 reserved for operating systems of the associated central processing unit each have two subregions 20(151A and 151B, and 152A and 152B,respectively) that are important for operation of a peer relationship.
The subregions 151A and 152A provide a list of the resources, i.e., input/output devices and reserved main memory unit regions, reserved for the associated 25central processing unit. Subregions 151B and 152B
provide the procedure by which the two central processing systems can communicate. In the preferred 1321~3~

embodiment, this communication is performed through subregion 155A of the portion of main memory reserved for usage by both the central processing unit~ 11 and 12 using a technique typically re~erred to as a data processing system mail box. In this technique, a message is left in the mail box 155~ by a ~irst central processing unit and a second central processing unit either reads the contents of the mail box periodically or is alerted by the first central processing unit that a message is available. Upon reading of the contents of the mail box 155A, the second central processing unit can make an appropriate response.
Referring now to Fig. 3, the principal components of the central processing unit interface device 30 are shown. The system bus 19 is coupled to system bus interface unit 17. The bus interface unit 17 has appropriate apparatus for identifying communications directed to the apparatus associated with the system bus interface unit 17 and for applying messages to the system bus 19 according to the protocol established for the system bus. The system bus interface unit 17 also includes ACK-NACK
(acknowledge-acknowledge not) decision unit 17A.
Communications from the system bus 19 are applied, through the system bus interface unit 17, to the input buffer registers 31, the status and control ~32~3~

logic unit 32, to the reserved memory unit 34, to the main memory protection unit 35 and to the input/output protection unit 3~. Signals from the status and control logic unit 32 are applied to the central processing unit 12 and to the system bus interface unit 17. The reserve memory unit 34 receives signals from the central processing unit 12 and applies (data) signals to the central processing unit 12. The main memory protection unit 35 and the input/output protection unit 3~ receive signals from the central processing unit 12 and apply signals to the system bus request unit 37. The system bus request unit 37, which includes the system bus output registers 37A, receives signals from the central processing unit 12 and applies signals to the central processing unit 12.
Referring next to Fig. 4, a block diagram of the components of a central processing unit 12 used in the preferred embodiment is shown. The principal processing function is performed by processor unit 41, an Intel 80386 component. The complex processing functions, such as floating point operations; are provided by coprocessor unit 43, implemented by an Intel 80387 component. The cache memory unit 44 provides access to the data required for processing by the central processing unit 12.
Referring next to Fig. 5, a block diagram of the 1321~3~

components of the status and control logic unit 32 are shown. The device identification register 51 contains identi~ication information for the central processing unit 12 coupled to the central processing unit interface device 30. The controller revision number register 52 identifies the functionality of the protection enforcement apparatus 30. The syndrome signal register 53 receives signals from the associated central processing unit that indicate an lo operational event having significance for the operation of the data processing system. The contents of the device identification register 51, the controller revision number register 52 and the syndrome signal register 53, in response to appropriate commands from the system bus interface unit 17, applies the register contents to the system bus interface unit 17. The software error register 54 is a status register for the software procedures.
The interrupt control register 55 includes interrupt status information such as the interrupt level of the currently executing program. Interrupt register 56 has information relating to a pending externally applied interrupt procedure stored therein. The software error register 54, the interrupt control register 55 and the interrupt register 56 can have data stored therein from signals in the system bus interface unit 17 and can apply the contents of the 1321~

registers to the system bus interface unit 17. In addition, the interrupt register 56 applie~ a signal to the associated central processing unit indicating that an interrupt i.~ pending. The privileged control register 57 and the unprivileged control register 58 contain control signals that are applied to and effect the operation of the associated central processing unit 12. Registers 57 and 5~ receive signals from the system bus interface unit 17. In the preferred embodiment, the unprivileged control register 58 is used for control of cache memory unit 44, while the privileged control register 57 applies signals to the associated processor 41 that impacts the operation.
Referring next to Fig. 6, the address buffer register 61 and the data buffer register 62 receive signals from the system bus interface unit 17 and apply the signals stored therein to dedicated RAM
(Random Access Memory) unit 63. Dedicated RAM memory unit 63 receives address signals from the associated central processing unit 12 and transfers data signals to the associated central processing unit 12. The dedicated memory unit 34 is used during the initialization procedure and is described below.
Referring next to Figure 7, a block diagram of the main memory unit protection device 35 and the input/output unit protection device 36 are shown. The 132~3~

input/output unit protection device address buffer register 77 and the input/output protection device data buffer register 78 receive signals from the system bus interface unit 17 and apply signals to the address input terminals and data input terminals respectively of input/output availability array 79.
The central processing unit address buffer unit 69 receives signals from the central processing unit 12 and applies signals to the address terminals of lo input/output unit availability array 79. The availability array 79 applies signals to the I~O
array decode unit 70. The signals from I/O array decode unit 70 are applied to system bus request un.it 37. The main memory unit protection device address buffer register 75 and the main memory protection device data buffer register 76 receive signals from the system bus interface unit 17 and apply signals to the address input terminals and the data input terminals respectively of the main memory unit availability array 72. The address input terminals of array 72 also receive signals from the central proce~ssing unit by means of the central processing unit address buffer register 71. The I/O-main memory transfer logic unit 74 receives signals from the central processing unit 12 and applies signals to the address signal input terminals of main memory unit availability array 72. The output signals from 132.~03~

availability array 72 are applied to main memory array decode unit 73, the decode unit 73 applies signals to the system bus request unit 37.
2. OPeration of the Preferred Embodiment In a ideal multiprocessor configuration, all of the central processing units would have access to all the resources of the data processing system without the requirement for protection mechanisms insuring the partitioning of resources among the central processing units. However, many operating systems do not have the procedures that prevent the attempts to access a resource assigned to another processor and/or are incompatible (non-homogeneous) the existing central processing unit(s) of the data processing system. The present invention provides the apparatus to permit an additional, non-homogeneous central processing unit to be treated by the other central processing unit(s) of a data processing system in a peer relationship, i.e., as if these protection mechanisms were present, by locating a central processing unit interface device 30 between the central processing unit 12 and the remainder of the data processing system, typically the system bus 19, that provides the appropriate protection. Thus, 25 if an updated version (release) of an operating system includes the protection mechanisms, then the (intermediate) central processing unit interface 132~3~

device 30 will not be necessary.
In the preferred embodiment, the host central processing unit 11 is a Honeywell Bull DPS6PLUS data processing system operating under control of the HVS1 operating system. The HVSl operating system includes procedures that provide for the trustworthiness of the system. In order to provide the data processing system with the capability of executing the wide repertoire of user programs using the UNIX operating lo system, the central processing unit 12, described in Fig. 4, was selected. The Honeywell Bull UCOSV
operatinq system, based on the UNIX operating system, has been provided for executing the user programs was believed to lack, at present, the appropriate mechanisms for secure partitioning of resources in the multiprocessor environment. The central processing unit interface device 30, illustrated in block diagram form in Fig. 3 is used to provide the protection mechanisms for the partitioning of resources.
Referring to the status and control logic unit of Fig 5, a host processing unit can control the operation of the data processing unit coupled to central processing interface unit 30 by entering data groups in appropriate registers and can obtain information concerning the coupled central processing unit by reading data groups in the registers. The 132103~

AC~ NACK decision unit 17A controls the access to the status and control logic unit 32 from the system bus 19. For example, when an attempt is made to enter an interrupt command in the interrupt register 56, the ACK-NACK decision unit 17A compares the interrupt level of the interrupt command with the current level of operation of the central processing unit 12 stored in interrupt control register 55. When the current operation level exceeds the interrupt level, then the ACK-NACK decision unit 17A applies an NACK
(ACKNOWLEDGE-NOT) signal to the system bus indicating that the interrupt command signal group has not been stored in the interrupt register 56. Similarly, the ACK-NACK decision unit will prevent the occurrence of possible conflicts by refusing to accept selected signal groups. In the preferred embodiment, access to the registers is typically through the system bus (by means of an I/O command). For example, the interrupt register 5~ can signal to the coupled central processing unit 12 the presence of an interrupt command stored therein, for the coupled central processing unit 12 to read the contents of the interrupt register 56, a I/O procedure is used.
The dedicated memory unit of Fig. 6 is used during the initialization procedure. Central processing unit 12, as illustrated in the embodiment of Fig. 4 has an initialization procedure that .' " ' ' . .

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addresses a portion of the main memory which the DPS~PLUS central processing system uses ~or its initialization procedure. In addition, the 80386 processor addresses main memory locations that are not (currently) implemented in the main memory unit 15. Therefore, during the initialization procedures for the data processing system, the initialization procedures needed to initialize ~boot) the 80386 central processing unit is transferred to the dedicated RAM unit via the system bus 19. Therea~ter, as the 80386 central processing unit begins its internal initialization procedures, although the addresses supplied from the central processing unit are main memory unit addresses, the addressed data is supplied from the reserved memory unit 34.
Referring to Fig. 7, the mechanism by which the access to the associated central processing unit 12 to data processing system resources is illustrated.
The input/output address buffer registers 77 and the input/output data buffer register 78 receive signals from data processing system that associate an input/output device address (i.e., channel number) with the availability of that input/output device (encoded as data) to the associated central processing unit 12. The encoded availability data is stored at the appropriate address in the availability register 79. When the associated central processing 13~1~3~

unit 12 attempts to access an input/output device, the address signals are applied to tho availability memory 79. The encoded data associated with that address is applied to the decode unit 70 and the decode unit 70 applies a signal to the system bus request unit that permits or prohibits the continuation of the access of the input/output unit.
Similarly, the main memory unit protection device 35, by means of the address buffer register 75 and the data buffer register 76 receive signals from the (system bus 19 of the) data processing system and store data signals encoded with information relating to the availability of the main memory unit 15 to the associated central processing unit 12. This information is stored at an address associated with a main memory address in the availability memory 72.
When the associated central processing unit 12 attempts to access the main memory unit 15, the address signals are applied, through address buffer register 71 to the availability memory 72~ The encoded data signals associated with that main memory unit address are then applied to decode unit 73. The decode unit 73 determines the availability of the addressed main memory location and applies appropriate signals to the system bus request unit 37. The address signals from the central processing unit 12 are stored in the system bus request unit 17 , .

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until the result of the decoding by decode unit 73 is completed. Tha output signals from decode unit 73 determines whether the access of the main memory unit lS can continue or is terminated in the system bus request unit 37. Input/output-main memory transfer logic unit 74 receives data signals from the associated central processing unit 12. In the event that an operation from the associated central processing unit involves a transfer of data between an input/output unit (e.g., 16)and the main memory unit 15, the availability of the input/output device 16 can be determined by address signals. However, the main memory location is encoded in the data signals. Transfer logic unit 74 determines the address in the main memory unit 15 to be accessed and applies this address to availability memory 72, thus controlling access to the main memory locations. As will be clear, this technique has the advantaqe that the availability of the main memory and the input/output units can be controlled, not only during an initiation procedure, but dynamically during the operation of the data processing system.
It will be clear to those skilled in the art that the peer processing configuration of the present invention relates to data processing system generally referred to as being "tightly-coupled". In this type of data processing system, the components of the data -25- 132103~
processing system are generally coupled without the intervention of a communication system or ~imilar format translation system.
It will be clear that the presence of the central processing unit interface device 30 provides the mechanism for secure partitioning of data processing system resources which permits the associated data processing unit to have a peer relationship with the other central processing units of the data processing system. The difference in the peer relationship of the present invention is that, even though the central processing unit which enters the data to be stored in the central processing unit interface device does not control the central processing unit associated with the central processing unit interface device the sense of a master/slave relationship, the entering data processing unit is required because its partitioning mechanism is secure (trustworthy). The central processing unit interface device, in response to the signals from the entering central processing unit, provides the secure (trustworthy) partiti~oning mechanism that is not present in the associated central processing unit.
The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.

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The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.

Claims (9)

1. A data processing system comprising:
at least a first and a second central processing unit, said first and said second central processing unit operating under control of non-homogeneous operating systems;
a plurality of data processing system resources, each of said resources being assigned to a selected one of said central processing units, wherein said first processing system includes an internal control means for preventing access to resources not assigned to said first data processing system; and external control means coupled between said second central processing unit and a remainder of said data processing system, said external control means to prevent access to data processing system resources not assigned to said second central processing system.

2. The data processing system of Claim 1 wherein said external control means includes means for altering said resources assigned to said second central processing unit.

3. The data processing system of Claim 2 wherein said means for altering is responsive to signals from said first central processing unit for determining resources assigned to said second central processing unit.

4. The data processing system of Claim 3 wherein said external control means includes means for storing and transmitting to said second data processing system initiation procedures.

5. The data processing system of Claim 4 wherein said external control means includes register means for storing control signals from said first central processing unit and for transferring said control signals to said second central processing system.

6. The data processing system of Claim 5 wherein said control signals include an interrupt signal.

7. The data processing system of Claim 1 further comprising interface means coupled between said data processing system and said external control means for providing signal groups to and for receiving signal groups from said data processing system that are compatible with signal groups of said first central processing unit and associated apparatus.

8. A data processing system of the type comprising at least first and second processing units and a plurality of resources, wherein said processing units and resources are coupled to a common signal transfer device for intercommunication, and wherein different ones of said resources are uniquely assigned for exclusive access by said first or second processing units; said system characterized by:
said first processing unit including as part thereof security apparatus for preventing access by said first processing unit to resources not assigned to said first processing unit; and interface apparatus connected between said common signal transfer device and said second processing unit for preventing access by said second processing unit to resources not assigned to said second processing unit.

9. The data processing system of claim 8, further characterized by:
said interface apparatus comprising:
protection means responsive to a resource identification supplied by said second processing unit when attempting to access the identified resource for determining whether said access should be permitted.