CN102646084A - Efficient network packet storage method implemented based on FPGA (field programmable gate array) - Google Patents
Efficient network packet storage method implemented based on FPGA (field programmable gate array) Download PDFInfo
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- CN102646084A CN102646084A CN2012100585675A CN201210058567A CN102646084A CN 102646084 A CN102646084 A CN 102646084A CN 2012100585675 A CN2012100585675 A CN 2012100585675A CN 201210058567 A CN201210058567 A CN 201210058567A CN 102646084 A CN102646084 A CN 102646084A
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Abstract
The invention relates to a method for storing various network packets (the number of types of the packets is more than 1) captured by users into an external memory, and the method is implemented based on an FPGA (field programmable gate array). The method is implemented by using a data read-write controller module, a data information cache region module and an external memory controller module. According to the invention, because an internal control logic is adopted for carrying out regionalization on the external memory according to capturing conditions set by users and implementing a data storage method, the maximum required memory bandwidth does not exceed a network bandwidth, so that the bandwidth demand of the external memory is greatly saved, thereby greatly reducing the difficulty of implementation and saving the implementation cost; and because the method is implemented through Verilog HDL (hardware description language), FPGA programming or an ASIC (application specific integrated circuit), various network packets captured on broadband networks (as high as 100G or above) can be subjected to a storage operation by using the most advanced semiconductor technology nowadays.
Description
[technical field]
The present invention relates to the data network communication technique field, refer in particular to a kind of implementation method that will store external memory storage into that realizes based on FPGA according to the variety of network data bag (kind of packet is greater than 1) that user's needs are caught.
[background technology]
Today; The internet has become necessary part in our daily life; Email, ecommerce, search engine, video are shared, SNS community etc. use in a large number and universal let us relies on the internet more; But enjoy the internet to we bring convenient the time; Can Virtual network operator and user be concerned about several problems: this network security? How is its performance? Just in case what if break down? How does service quality guarantee? The solution of these a series of problems all depends on network test, depends on the packet that extraction is relevant with it from network system and analyzes.And before these packets are analyzed, because data volume is big and the restriction of PC processing power, all need be in external memory storage with these metadata caches.
Traditional method is that the data after catching are directly stored in the external memory storage, and the benefit of doing like this is exactly simple, thereby this method is simple in network system, is feasible when network speed is lower.But unification of three nets and increasing application make network system become increasingly complex, and also therefore are easy to occur the situation that a network packet meets a plurality of conditions of user's setting.We suppose that the user has set A, two conditions of B, and data need store in the external memory storage, just have after a packet is come so in four maybe: eligible A, eligible B, condition A and B meets, condition A and B do not meet.Except the 4th kind need not stored, other three kinds all needed storage, so just need 3 times memory bandwidth to go to store the data of catching like this; After if the user sets three conditions of ABC, just need 7 times memory bandwidth to go to store the data of catching; Four conditions are corresponding is 15 times memory bandwidth.N the reality 2 that condition is corresponding
n-1 times memory bandwidth demand.At network speed up to 100Gbps; Today among the network system of 400Gbps being is also is being researched and developed, when network speed was 100G, 15 times of memory bandwidths just meaned 1500Gbps; Obviously; Make and store packet that the user the catches difficulty all the more that just seeming in this way, even finally realized, also can be because of with high costs and lose practical value.
So industry presses for a kind of more efficient, more economical various packets that the user is caught as required and stores the method in the external memory storage into.
[summary of the invention]
To the deficiency of prior art, the invention provides a kind of hardware implementation method based on scale programmable logic device (FPGA).The characteristics of FPGA are to use very flexible, can programme to FPGA as software through the VerilogHDL language and realize the function that the user needs, and have the advantage of the high speed of hardware circuit simultaneously again.Utilize this method the packet that the user catches to be stored in the external memory storage with the memory bandwidth that is no more than network speed.
In order to achieve the above object, the present invention has adopted following technical scheme:
The present invention adopts the hardware implementation mode based on FPGA, also can change into by ASIC and realizing.
The external memory storage that is connected with FPGA that the present invention adopts includes but not limited to DDR RAM, QDR RAM and RLDRAM.
The present invention includes 3 modular assemblies:
Build a data read-write controller module in the FPGA, after receiving write data requests, respectively package informatin and packet are delivered to the appointed area of canned data buffer area according to writing solicited message; After receiving read data request, read request is delivered to the appointed area of canned data buffer area module according to read request information.
Build a data message buffer area in the FPGA; The N sub-module is arranged in it is characterized in that; The span of N is 2 to 63, and a subregion of each submodule and external memory storage is corresponding, be used to control external memory storage subregion, each subregion data buffer memory, calculating and store each subregion stored valid data bag number; The length of each bag, each wraps in the initial address message (IAM) of exterior storage.
Build an external memory controller module in the FPGA, be divided into two parts of read-write: when carrying out write operation, according to writing the entry address, write data length deposits data in the external memory storage of assigned address; When carrying out read operation, according to reading in port address, read data length is read from the external memory storage of assigned address data with data, and adds packet header bag tail signal output.
What carry out subregion to external memory storage and realize the storage means of data the contact conditions that the present invention because adopted is set according to the user by inner control logic; So it can not surpass the network bandwidth to memory bandwidth demand maximum yet; So just saved the exterior storage bandwidth demand greatly; Thereby greatly reduce the realization difficulty, also practiced thrift the realization cost; Realize through FPGA programming or ASIC owing to adopted, so can utilize current state-of-the-art semiconductor technology to carry out data storage operations up to the variety of network data bag of catching on 100G or the above broadband network through Verilog HDL language.
[description of drawings]
Fig. 1 is a kind of high-efficiency network packet storage means logical process system chart of realizing based on FPGA in the embodiment of the invention.
Fig. 2 is a kind of high-efficiency network packet storage write data control synoptic diagram of realizing based on FPGA in the embodiment of the invention.
Fig. 3 is that synoptic diagram is upgraded in a kind of high-efficiency network packet storage write data control information that realizes based on FPGA in the embodiment of the invention.
Fig. 4 is a kind of high-efficiency network packet storage means data read synoptic diagram of realizing based on FPGA in the embodiment of the invention.
[embodiment]
Below in conjunction with accompanying drawing and embodiment, technical scheme of the present invention is done further elaboration.
With reference to figure 1, a kind of high-efficiency network packet storage means logical process system chart of realizing based on FPGA in the embodiment of the invention.Set A, two conditions of B this supposition user, so we get 3 with N, also be about to external memory storage and be divided into 3 (2
2-1) individual subregion, wherein condition A and B meet and are stored in 1 subregion, and only A meets is stored in 2 subregions, and only B meets is stored in 3 subregions, all incongruent data packet discarding.
Because the read-write operation of data storage is relatively independent, therefore separately set forth for read-write.
For the write operation of data storage, whole process was divided into for 3 steps:
The first step, in Fig. 1, this part operation is accomplished in data read-write control device module.This module will be write among the FIFO from the Frame of data capture module in complete depositing in, wait to receive a complete data frame indicator signal after, as shown in Figure 2; Judge according to capturing information; All meet for condition A and B, complete Frame data are read from write FIFO, and will put height the FIFO1 signal of writing of data message buffer memory 1 subregion; After treating that whole frame data run through, the request of sending the information cache 1 subregion control information RAM1 that Updates Information; Meet for A only, complete Frame data read from write FIFO, and will put height the FIFO2 signal of writing of data message buffer memory 2 subregions, treat that whole frame data run through after, the request of sending the information cache 2 subregion control information RAM2 that Update Information; Meet for B only, complete Frame data are read from write FIFO, and will be to after the writing the FIFO3 signal and put height and treat that whole frame data run through of data message buffer memory 3 subregions, the request of sending the information cache 3 subregion control information RAM3 that Update Information; For condition A and all incongruent packet of condition B, then abandon.
In second step, in Fig. 1, this part operation is accomplished in data message buffer area module.This module can will be from the data information memory of data read-write control device in corresponding FIFO according to the write signal of corresponding FIFO, and the computational data bag is long.After the request of receiving from the lastest imformation buffer memory N subregion control information RAMN of data read-write control device; As shown in Figure 3; Packet length information is deposited among the RAMN of current address; The RAMN write address adds 1 then, sends the N subregion simultaneously to outside memory write data request signal and to the entry address of outside memory write data, behind the read signal that detects metadata cache FIFON, calculates and the next entry address that is deposited into external memory storage of wrapping of renewal according to current pack is long.
In the 3rd step, in Fig. 1, this part operation is externally accomplished in the memory control module.This module is detecting the N subregion behind outside memory write data request signal; Data are read from the FIFON of data message buffer area module, and the entry address to outside memory write data that provides according to data message buffer area module again is deposited into data in the external memory storage.
Read operation for data storage; Concrete operations are as shown in Figure 4; After detecting the data read request signal that the cpu i/f module sends over; The data read-write control device is judged the N district reading of data from external memory storage according to the data read request information that the cpu i/f module sends over; And the packet number that the up-to-date address of the corresponding RAMN of read data information buffer memory is read as needs; Reading of data packet length and calculate the port address that reads in of next packet on this basis from RAMN then after data read out, is given the cpu i/f module with data after also need adding packet header and bag tail information to data according to data packet length from external memory storage.
More than combine the accompanying drawing specific embodiments of the invention to be described; But these explanations can not be understood that to have limited scope of the present invention; Protection scope of the present invention is limited the claims of enclosing, and any change on claim of the present invention basis all is protection scope of the present invention.
Claims (10)
1. high-efficiency network packet storage means that realizes based on FPGA; Comprise the data read-write control device; Three parts of data message buffer zone and external memory controller are formed; It is characterized in that; The data read-write control device is delivered to the data message buffer zone according to read write command with packet and packet information, and the data message buffer zone is used for the control of external memory partition and the processing and the storage of each subregion storing data information, and the external memory controller module is used for reading and writing data from external memory storage.
2. data read-write control device as claimed in claim 1 is characterized in that, after receiving write data requests, respectively package informatin and packet is delivered to the appointed area of canned data buffer area according to writing solicited message; After receiving read data request, read request is delivered to the appointed area of canned data buffer area module according to read request information.
3. data message buffer area as claimed in claim 1 has the N sub-module in it is characterized in that, the value of N is by formula 2
n-1 confirms, wherein n is the number of the contact conditions of user's setting, and value is 2,3,4,5,6, and the respective partition of each submodule and external memory storage is corresponding respectively.
4. external memory controller module as claimed in claim 1, it is characterized in that being divided into two parts of read-write: when carrying out write operation, according to writing the entry address, write data length deposits data in the external memory storage of assigned address; When carrying out read operation, according to reading in port address, read data length is read from the external memory storage of assigned address data with data, and adds packet header bag tail signal output.
5. read-write requests information as claimed in claim 2 is characterized in that it is continuous numerical value, and the value minimum is 0, is the formula 2 in the claim 3 to the maximum
n-1 value, wherein numeral 1 to 2
n-1 respectively representative carry out the zone that read-write requests is operated, 0 this read-write operation of expression is invalid.
6. appointed area as claimed in claim 2; Be the described submodule of claim 3, it is characterized in that the value of the described read-write requests information of claim 2, the different different submodules of value representative; Represent first submodule such as 1; 2 represent second sub-module, so analogize, and 63 represent the 63rd sub-module.
7. submodule as claimed in claim 3 is characterized in that each submodule by a RAM, and FIFO and steering logic are formed, and wherein FIFO is used for the buffer memory of packet, and RAM is used to store the length of each bag, and each wraps in the initial address message (IAM) of external memory storage.
8. steering logic as claimed in claim 7 is characterized in that this logic comprises that two parts form: write control logic with read steering logic.
9. write control logic as claimed in claim 8; It is characterized in that this module is used to calculate the packet number that writes this module; The write address of RAM, the bag of current data packet is long, according to the long externally entry address of storer of next packet of calculating of the bag of packet; And will control the entry address of this packet and the bag long of packet writes among the RAM, the control external memory controller writes the data packet the entry address of appointment.
10. the steering logic of reading as claimed in claim 8; It is characterized in that number according to packet wraps into port address information with packet length information and external memory storage and reads out from RAM, the control external memory controller reads out packet from the entry address of appointment.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103838679A (en) * | 2012-11-22 | 2014-06-04 | 中兴通讯股份有限公司 | Caching processing method and device |
| CN104657287A (en) * | 2015-02-12 | 2015-05-27 | 成都大公博创信息技术有限公司 | Novel data caching system and caching method for broadband receiver |
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| CN101572891A (en) * | 2009-06-15 | 2009-11-04 | 东南大学 | System and method for filtering 3G data packet based on FPGA |
| CN101908031A (en) * | 2010-07-23 | 2010-12-08 | 四川九洲电器集团有限责任公司 | FPGA-based enhanced serial port |
| CN102096648A (en) * | 2010-12-09 | 2011-06-15 | 深圳中兴力维技术有限公司 | System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) |
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2012
- 2012-03-06 CN CN2012100585675A patent/CN102646084A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101572891A (en) * | 2009-06-15 | 2009-11-04 | 东南大学 | System and method for filtering 3G data packet based on FPGA |
| CN101908031A (en) * | 2010-07-23 | 2010-12-08 | 四川九洲电器集团有限责任公司 | FPGA-based enhanced serial port |
| CN102096648A (en) * | 2010-12-09 | 2011-06-15 | 深圳中兴力维技术有限公司 | System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838679A (en) * | 2012-11-22 | 2014-06-04 | 中兴通讯股份有限公司 | Caching processing method and device |
| US9563584B2 (en) | 2012-11-22 | 2017-02-07 | Zte Microelectronics Technology Co., Ltd. | Method and device for buffer processing in system on chip |
| CN103838679B (en) * | 2012-11-22 | 2017-08-04 | 中兴通讯股份有限公司 | A kind of method for caching and processing and device |
| CN104657287A (en) * | 2015-02-12 | 2015-05-27 | 成都大公博创信息技术有限公司 | Novel data caching system and caching method for broadband receiver |
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Application publication date: 20120822 |