DE10036627A1 - Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit - Google Patents

Abstract

The circuit (1) has a number of adjacent cells (2a-2e) divided into at least 2 cell types, the cells having a sufficient size for integration of a number of logic elements (3a,3e), at least some of the cells having programmable logic elements. The terminals (5a-5d) for the interconnections between the cells are positioned to allow mixing of the different types of cells within the cell matrix. An Independent claim for a design method for an integrated cell matrix circuit is also included.

Description

The present invention relates to an integrated circuit circle according to the preamble of the independent claim. In order to the present invention is generally concerned with the manufacture position of logical semiconductor components.

From DE 44 16 881 C2, the disclosure content of which by Be access is fully integrated is a procedure to operate a data processing device with program mier- and configurable cell structure known. The dates processing device comprises a cell matrix from a A large number of homogeneous structures arranged orthogonally to each other cells, which are free in their function and networking are programmable. It is not specified, as in Pra xis an integrated module with this cell matrix advantage can be manufactured. It also does not specify like the data processing device shown in simple  Manufactured adapted for certain applications that can.

From "Principles of CMOS VLSI Design" by NH Weste and K. Eshraghian, Addison-Wesley, 2nd edition 1993 , chapter 8, section 8.4.2.1 , a block layout, ie a floor plan of a generic, ie adaptable to certain applications, PLA is known , An illustration is shown in which a row of cells for different logical functions are arranged side by side. It is further shown in Fig. 8.80 of the document a physical implementation for a PLA, in which two different logic function blocks are provided with differently made connections. Here, too, it is not specified how an integrated module can be produced particularly advantageously in practice.

It is desirable to use integrated circuits, in particular highly complex such as that described in DE 44 16 881 C2 physically implement a simple way and to be able to adapt.

The object of the invention is new for the ge to provide advertising application.

The solution to this problem is claimed independently. before preferred embodiments can be found in the subclaims.

According to a first aspect of the present invention with suggested that with an integrated circuit several adjacent cells, at least two Types of cells are provided, which have connections sen, it is provided that the cells are used to integrate a  Large number of logical elements are of sufficient size, where at least some of the cells have at least one logical Element is programmable and the connections at least in essential corresponding positions of the cell vorese hen to be such an arbitrary, H. not strictly re gular repeated cell types mixing to allow in the adjacent arrangement of the cells.

A first essential idea of the invention is therefore in that an integrated highly complex circuit, on a variety of different logical functions is realized, can be easily produced by then cell blocks are defined that are in the cell area have programmable logic elements and externally have the same arranged connections. because at it was recognized that it was solely because of the fact that between areas chen for the implementation of certain functions on prep it was the right way to shape conductor tracks with no actual function of connecting lines are provided, the number of when Chip design to be considered objects is increased, different cell types at any point becomes possible to be arranged on the integrated circuit without the complete circuit can be designed from scratch got to.

In the integrated circuit, at least one the cell types have at least one storage point, floating point Arithmetic unit, integer arithmetic unit, adder, multiplier, Encryption, connection, input and / or output medium realized. With the encryption or crypt topography can be, for example, a circuit act structure that is fixed or programmable the bits of a Data word exchanged for encryption or decryption  make. With a lanyard be provided that supplied signals without any Ver change brought out on an opposite cell side become; there are z. B. exclusively continuous conductor tracks are provided. If storage means can be provided, it can be a RAM, ROM, PROM, EEPROM memory and / or combinations of the aforementioned memory act guys. The input and / or output means can be in integrated circuits for computer technology for communication cation with a modem connection, a network connection, a Storage means and / or with a peripheral device connection such as a mouse, printer, display, etc.

The cells are preferred for the integration of little at least 100, preferably 1000 logical elements, in particular Gates must be dimensioned. This ensures that the too additional additional space for the provision of Ver binding lines of the cells are not significantly disadvantageous affects and at the same time strongly different cell functions are realizable. It is particularly possible, at least to provide two different cell types, each at least 100, preferably 1000 logical gate equivalents. here it should be mentioned that, obviously, more than two under different cell types on a uniformly manufactured, continuous substrate on which the integrated circuit circle is formed, can be arranged.

The cells can preferably be dimensioned such that at least an edge length of the cells at least 500 times before adds at least 1000 times the cha manufacturing process characterizing gate length. At a manufacturing process with which 0.25 µm structures can be produced thus have a cell edge at least a length of 125 microns.  

It is preferred if both edges of the cell have a certain one Do not fall below the minimum size. At least you can two edge lengths of the cells at least 200 times before adds at least 500 times the cha manufacturing process characterizing gate length.

It is preferred if the cells are of different types least have essentially identical sizes, ie all if there are non-significant size deviations.

The connections are preferably at least one of the connections se supply voltage and / or ground, and / or at least one ne include cell input and / or output line, it ins It is particularly possible that the cell input and / or output device forms part of an input and / or output bus and / or a clock line. In this case, the for each bit provided feeds and / or derivatives on each because there are enough corresponding places along the cell be arranged on the wall. This allows two or more independent buses brought to the cell run through and / or through it without any signal transfer problems become relevant.

It is preferred to attach at least some of the cell connectors Arrange cell edge. This allows a tile-like coexistence rearranging the components, which is technically good is stig. The tile-like juxtaposition is before moves without overlapping the individual elements achieved what that Layout further simplified. The connections are full constantly led to the edge, so that connections on the mask adjoin neighboring cells and in the integrated Merge circuit into one another.  

Alternatively and / or additionally, at least some of the Cell connections arranged on the top and / or bottom of the cell be nice. This allows at least two layers of cells over to provide each other. With a cell structure according to DE 44 16 881 can in particular the arithmetic units such as multipliers, Adders etc. in a first position and the associated Tax machines, d. H. Statemachines, in the second position be ordered.

The invention is described below only by way of example Drawing explained. In this shows:

Fig. 1 shows an integrated circuit of the present invention;

Figure 2 is a detail of the integrated circuit with a single cell.

Fig. 3 different cells of the inte grated circuit according to the invention with respective logical elements.

According to Fig. 1, a 1 generally designated inte grated circuit 1 a number of different types of cells 2 comprises a- 2 e with respective logic elements 3 a- 3 e. The individual cells are delimited from one another, as illustrated by boundary lines 4 . Connections 5 a - 5 d are provided on the cells, which connect cells 2 a - 2 e across the boundary lines to the respective neighboring cells or to the outside.

The cells 2 a are memory cells 2 a which are designed for the optional storage of data, ie for reading and / or writing operations. Cell 2 b is an I / O cell 2 b, ie an input / output unit cell 2 b. The I / O cell 2 b is designed to input and / or output to one or more peripheral devices such as a mouse, a trackball, a touch pad, a printer, a modem, a camera, a display device and / or a graphics card. The cells 2 c are floating point unit cells 2 c, ie floating point unit cells 2 c, which are designed to perform floating point arithmetic operations on data which represent floating point numbers. The cells 2 d are arithmetic unit cells 2 d which are designed to carry out logical operations and arithmetic operations on data which present logical operands or integers re. The cells 2 e are multiplying cells 2 e, which multiplicatively link data representing numbers.

Each of the cells 2 a to 2 e is made up of a plurality of gates (not shown) in a manner known per se. These gates form the logic elements 3 a - 3 e of the cells. At least some of the gates are programmable in each cell during the runtime in order to be able to perform a required task with the cell.

The boundary lines 4 between the cells do not have to be implemented by a real structure. Rather, they can be defined by a gap between the closely spaced gates and on their components of the cells 2 a to 2 e and only crossed by the lines of the connections 5 , which, with a good design, may have a slight expansion. The possibly only imaginary boundary lines 4 can be arranged so that the individual cells 2 a to 2 e have at least substantially identical sizes. The boundary lines 4 form a rectangle 6 circumscribing the respective cell 2 , which has sides 4a-4d, cf. Fig. 2.

According to FIGS. 2 and 3 on each of the sides 4a to 4d on connections 5 a-5 d provided that the cells 2 a- 2 e with the respective neighboring cells, or lead connect from the integrated circuit to the outside and / or the outside of the outer cells of the integrated circuit 1 are completed in a suitable manner.

Terminal 5 a represents a from input lines 7a and off output lines 7 b existing bus connection 5 a represents. Terminal 5 c represents a from input lines 8 b and the output lines 8 a existing bus connection 5 c. In the interior of the cell 2 switch d are provided to optionally to transfer data from the input lines 7 a of the bus connection 5 a to the output lines 8 a of the bus connection 5 c and / or to transmit other data with the same data format to the output lines 8 a. An internal bus 9 is thus provided. The input lines 7 a and the output lines 8 a are led directly to the cell edge defined by the boundary line 4 a or 4 c. The input lines 7 a are equal to the respective output lines 8 a that lines 8 a of the first cell with input lines 7 a of the second cell are in electrically conductive connection when two cells are arranged side by side.

In a corresponding manner, output lines 7 b are provided at connection 5 a, which correspond to input lines 8 b of connection 5 c as previously explained for the input / output line pair 7 a, 8 a. Further, provided on the side 4b of input and output lines correspond to the terminal 5 b with output and input lines of the Anschlus ses 5 d of the side 4d.

Inside the cell 2 d are an arithmetic unit 10 for linking data running on the input lines of the connections 5 and an associated automatic control unit 11 and a series of internal connections 12 a to 12 c between them and for connecting the same to the bus 9 provided in a manner known per se.

According to FIG. 3, the cells 2 a to 2 e of the different cell types have identical sizes as illustrated by the identical size of the boundary lines 4 circumscribing the cell. The connecting lines 5 of all cells 2 a to 2 e are each brought up to the cell boundary 4 , where they are in the same positions. The internal connections between the connections 5 on a cell 2 to one another and to the logical elements provided in the cell can vary from cell to cell.

The integrated circuit of the present invention is manufactured as follows:

First, the memory capacities, computing power, input-output requirements, etc. of the integrated circuit 1 required for a specific application are determined. Then it is determined with which circuits such as memory, floating point arithmetic, integer arithmetic, adder, multiplier, encryption, connection, input and / or output circuits etc. these functions can be implemented. These circuits are now summarized in blocks to define respective cell types, e.g. B. RAM cells (memory cell for random access), I / O cells, floating point unit cells, arithmetic unit cells, multiplying cells, etc. If necessary, it is checked whether these functions are already provided for previously manufactured integrated circuits were. An attempt is made to distribute the desired functions over different cell types in such a way that all cell types have an at least approximately a same area requirement. The cell type with the highest space requirement determines the size of all cell types.

After the division of functions into different cell types 2 a to 2 e, the connecting lines 5 required between the cells are determined. Then a spatial arrangement of the connection lines 5 to the cells is determined. The cells of the respective cell types 2 a to 2 e are then designed in each case without being influenced by the design of the other cell types. In this case, 2 line connections 5 are placed from the inside of the cells to the cell edge 4 . Of the gates provided in the various cell types, at least some are designed in each cell so that they are programmable during runtime in order to be able to perform a task with the cell that is required in each case. This is the case if the connection structure can be changed, ie the evaluated connections and / or the function of an arithmetic unit etc. can be changed.

This happens for all cell types one after the other, unless designs for previously manufactured integrated circuits can be used. If it turns out that the space required for the largest cell type is not sufficient, all cells can be enlarged simply by extending the connecting lines 5 accordingly. In particular, this enables large groups to design all cell types simultaneously.

It then becomes the functionality of each individual cell type checked for itself without the functionality of others Cell types should be checked at the same time. Reduce this the total computing effort for checking the inte Integrated circuit essential and thus enables one design of highly complex circuits is inherently regular repeating, even complex units.

After the draft of the last to be completed An overall design is drawn up in which the ver different cell types are placed side by side so that the corresponding input and output lines in electrical conductive connection. After that, if necessary checked the electrical connections between the cells. The review effort for this is also very low.

If necessary, further, non-repetitive Units are provided, such as surge protection circuits. The seals, d. H. Chip terminations, line terminations for on the switch connecting lines, test structures, etc. located at the edge of a circle can for an actual design of a circuit according to DE 44 16 881 C2 a single configuration manager is provided the one that differs from the other cell types has circuit arrangement.

In this way, an integrated circuit for one specific purpose designed in a very short time and forth position will be given. The production itself then takes place in a conventional way.

It should be noted that in addition to or instead of the cell types shown in FIGS . 1 and 3, others can also be used.

For example, it is possible to use two different ones instead cell types, the first of which are floating point operations and the second arithmetic operation of integers leads to implementation, just a single cell type to provide these functions with both types of operations can be executed.

It should be noted that the cells are not mandatory must be square. In particular, there are others Other cell forms can be used, which one Allow overlapping or side-by-side arrangement. So the use of hexagonal or triangular cells is conceivable. It is also conceivable to mix two or more cell forms, z. B. Triangles with trapezoids. Then the connections are on the cell boundaries for all cell forms so that a neighborly arrangement of different cell forms like desired is possible. So the connections are also there at at least substantially identical positions of the Cell, so as to contribute to the mixing of cell types according to the invention to allow the adjacent arrangement of the cells.

It should be noted that the corresponding inputs and output lines on adjacent sides of the cells do not necessarily have to be connected via a bus structure. So in particular it is possible to use other than the one Data fed in on the opposite page ben. The data can e.g. B. changed by the calculator become.  

LIST OF REFERENCE NUMBERS

1

integrated circuit

2

cell types

2

a RAM cell (memory cell for random access)

2

b I / O cell (input-output unit cell)

2

c Floating point unit cell (floating point unit cell)

2

d calculator cell (ALU)

2

e Multiplying cell

3

logical elements of the cells

2

a-

2

e

4

cell border
4a, b, c, d sides of the cell

5

Connections to the cells

2

5a, b, c, d bus connections on the sides

6

circumscribing square

6

7

a Input lines on the bus connection

5

a

8th

a Output lines on the bus connection

5

c

9

internal bus

10

Calculator of the cell

2

d

11

Machine control

11

the cell

2

d

12

internal connections in cell

2

d

Claims (17)

1. Integrated circuit with a plurality of cells which are adjacent to one another, at least two types of cells being provided which have connections, characterized in that the cells have a size which is sufficient for integrating a large number of logic elements, at least on at least some of the cells a logic element is programmable and the connections are provided at at least substantially identical positions of the cell, so as to allow a mixture of cell types in the adjacent arrangement of the cells. 2. Integrated circuit according to the preceding claim characterized in that with at least one of the cells larten at least one memory, floating point Arithmetic unit, integer arithmetic unit, adder, multiplier,  Encryption, connection, input and / or Output means is realized. 3. Integrated circuit according to the previous type saying, characterized in that at least one of the Cell types a RAM, ROM, PROM, EEPROM storage means and / or combinations of the aforementioned storage types. 4. Integrated circuit according to one of claims 2 or 3, characterized in that at least one of the cells larten an input and / or output means for communication with a modem connection, a network connection, a Storage means and / or with a peripheral device finally realized. 5. Integrated circuit according to one of the preceding Claims, characterized in that the cells for the Integration of at least 100, preferably 1000 logical Elements, in particular gates are dimensioned. 6. Integrated circuit according to one of the preceding Claims, characterized in that at least two Different cell types are provided, each of which at least 100, preferably at least 1000 logic gates equivalent. 7. Integrated circuit according to one of the preceding Claims, characterized in that at least one Edge length of the cells at least 500 times, preferred at least 1000 times the cha manufacturing process characterizing gate length. 8. Integrated circuit according to one of the preceding Claims, characterized in that at least two Edge lengths of the cells at least 200 times, preferred  at least 500 times that of the manufacturing process characterizing gate length. 9. Integrated circuit according to one of the preceding Claims, characterized in that the cells ver different species, at least essentially identical Have sizes. 10. Integrated circuit according to one of the preceding Claims, characterized in that the connections to at least one of the connections supply voltage and / or Mass, and / or at least one cell input and / or output line include. 11. Integrated circuit according to the previous type saying, characterized in that the cell inputs and / or output line part of an input and / or Output bus and / or includes a clock line. 12. Integrated circuit according to the previous An saying, characterized in that the cell inputs and / or output lines at least two of each other separate buses include. 13. Integrated circuit according to one of the preceding Claims, characterized in that all correspond appropriate connections of the different cell types to each because the same positions are arranged. 14. Integrated circuit according to one of the preceding Claims, characterized in that at least some the cell connections are arranged at the cell edge. 15. Integrated circuit according to the previous An saying, characterized in that a plurality of Cells are arranged side by side.   16. Integrated circuit according to one of the preceding Claims, characterized in that at least some the cell connections on the cell top and / or bottom is arranged. 17. Integrated circuit according to the previous An saying, characterized in that at least two layers Cells are provided one above the other.