DE19926538A1 - Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component - Google Patents

Abstract

The hardware has a decoupled configuration register and performs programs on a component with a single or multi-dimensional cell structure. Data flow or control flow graphs are partitioned into time-separated sub-graphs and formed sequentially and implemented on the component. An Independent claim is also included for a method for performing programs on a component with a single or multi-dimensional cell structure.

Description

Object of the invention and areas of application

The present invention extends to the field of programmable and especially during operation reprogrammable arithmetic and / or logical Blocks with a large number of arithmetic and / or logical Units whose interconnection is also programmable and is reprogrammable during operation. Such logical Blocks are under the generic term FPGA of different Companies available. There are also several patents published using special arithmetic blocks automatic data synchronization and improved disclose.

All of the blocks described have a two or multi-dimensional arrangement of logical and / or arithmetic units that are connected to each other via bus systems are interconnectable.

The object of the invention is to provide a programming method for To make available that enables the described Blocks in common high-level languages efficiently program while taking advantage of the variety parallelism of the units described Building blocks largely automatically, completely and efficiently use.

State of the art

Blocks of the type mentioned are mostly programmed using ordinary data flow languages. There are two basic problems:

• 1. Programming in data flow languages is for Programmer needs getting used to, deeply sequential tasks can only be described with great difficulty.  
• 2. Leave large applications and sequential descriptions with the existing translation programs (synthesis Tools) only to a limited extent on the desired target technology (synthesize).

Applications are usually partitioned into several sub-applications, which are then synthesized individually for the target technology ( FIG. 1). The individual binary codes are then loaded onto one block each. An essential prerequisite of the invention is the method described in DE 44 16 881, which makes it possible to use several partitioned sub-applications within a module by analyzing the time dependency and sequentially requesting the sub-applications required in each case from a higher-level loading unit and then by the latter be loaded onto the block.

Existing synthesis tools are only able to map program loops to blocks to a limited extent ( Fig. 2 ( 0201 )).

So-called FOR loops ( 0202 ) are often also supported as a primitive loop by rolling the loop completely onto the resources of the target module.

In contrast to FOR loops, WHILE loops ( 0203 ) do not have a constant termination value. Rather, a condition evaluates when the loop is aborted. Therefore, it is usually not known (if the condition is not constant) at synthesis time when the loop breaks. Due to the dynamic behavior, synthesis tools cannot permanently map these loops to hardware, ie they can be transferred to a target block.

In general, recursions cannot be mapped to hardware, when the recursion depth is not known at the time of synthesis and so that is constant. When recursing, with each new one Recursion level allocated new resources. That would mean, that new hardware is available with every recursion level must be asked, which is not dynamically possible.

Even simple basic structures are only available from synthesis tools can be mapped if the target module is sufficiently large, d. H. offers sufficient resources.

Simple time dependencies ( 0301 ) are not partitioned into several sub-applications by today's synthesis tools and can therefore only be transferred as a whole to a target module.

Conditional executions ( 0302 ) and loops via conditions ( 0303 ) can also only be mapped if sufficient resources exist on the target block.

Method according to the invention

It is by the method described in DE 44 16 881 possible conditions at runtime within the Recognize hardware structures of the named modules and to react so dynamically that the function of the Hardware modified according to the condition becomes what is essentially by configuring a new one Structure happens.

An essential step in the method according to the invention is the partitioning of graphs in time-independent Subgraphs.  

The term "temporal independence" is defined that the data transferred between two sub-applications are through a memory, of whatever configuration (also using simple registers). The is particularly possible at the points on a graph where a clear interface with a limited and possible minimal amount of signals between the two There are partial applications.

The temporal independence can be brought about in large graphs by deliberately inserting clearly defined and possible simple interfaces for storing data in a buffer (cf. S _n in FIG. 4). Loops are fundamentally very independent of time, because they work for a long time over a certain amount of (mostly) local variables in the loop and only require the operands or the result to be transferred when the loop enters and exits the loop.

The independence in time ensures that after the complete execution of a partial application subsequent partial application can be loaded without any other dependencies or influences occur. When saving the data in the named memory, a Signal (trigger) are generated by the parent Loading unit for reloading the next partial application prompts. The trigger can be used when using simple Registers are always generated as memory when that Register is described. When using memories, i. b. of those that work according to the FIFO principle is the Generation of the trigger depends on several conditions.  

For example, the following conditions can generate a trigger individually or in combination:

• - Results memory full
• - operand memory empty
• - no new operands
• - Generated any condition within the sub-application through z. B.
• - comparator
• - Counter.

A partial application is also called module in the following intelligibility from the perspective of classic programming to increase. For the same reason, signals are as follows also called variables. The variables differ essentially different from conventional variables in one point: everyone Variable is assigned a status signal (ready), which indicates whether the variable has a valid value. If a signal has a valid (calculated) value, that is Status signal Ready; if the signal is not a valid value owns (calculation not yet completed), that is Status signal Not_Ready. The principle is detailed in the Patent application PACT02 described.

The processor model

The graphs shown in the following figures have as Graph nodes always in module, assuming that several modules are mapped to a target module can. That is, although all modules are in time are independent, only after the modules one Reconfiguration carried out, or a data storage inserted, marked with a vertical line and Δt are. This point is called the time of reconfiguration.  

In summary, this means:

• 1. Large modules can be partitioned at appropriate locations and in small, time-independent modules be disassembled.
• 2. In the case of small modules that are common to one Target module can be mapped to the temporal Independence waived. This will Configuration steps saved and data processing accelerates.
• 3. The reconfiguration times are according to the Positioned resources of the target building blocks. This is one given any scaling of the graph length.

In Fig. 4a some basic characteristics of the process of the invention are shown:
The modules of type A are grouped together and end up with a conditional jump, either to B1 or B2. At this position ( 0401 ) a reconfiguration point is inserted, since it makes sense to consider the branches of the conditional jump as a group (case 1). If, on the other hand, both branches of B (B1 and B2) match A on the target module (case 2), it would make sense to insert only one reconfiguration point at 0402 , as this reduces the number of configurations and increases the processing speed. Both branches (B1 and B2) jump to 0402 .

The configuration of the cells on the target module is shown schematically in FIG. 4b. The functions of the individual graph nodes are mapped to the cells of the target module. One line each represents a configuration. The dashed arrows when changing lines indicate a reconfiguration. S _n is a data-storing cell of any configuration (register, memory, etc.). S _n I is a memory that accepts data and S _n O outputs a memory of the data. The memory S _n is the same for the same n, I and O denote the data transfer direction.

Both cases of the conditional jump (case 1, case 2) are shown.

The model in FIG. 4 corresponds to a data flow model, however with the essential expansion of the reconfiguration point and the partitioning of the graph that can be achieved thereby, the data transferred between the partitions being buffered.

In the model of FIG. 5a, a graph from a set of graphs B is selectively called up from any graph set and constellation ( 0501 ). After executing B, the data return to 0501 .

If a sufficiently large sequencer (A) is implemented in 0501 , the model can implement a principle very similar to that of typical processors. Get there

• 1. Data in the sequencer A, which it decodes as commands and reacts to it according to the "von Neumann" principle;
• 2. Data in the sequencer A that are considered data and to a permanently configured arithmetic unit C for the calculation to get redirected.

Ver Graph B selectively provides a special arithmetic unit and / or special opcodes for certain functions and is alternatively used to accelerate C. For example, B1 can be an optimized algorithm for calculating matrix multiplications, while B2 represents an FIR filter and B3 represents a pattern recognition. The appropriate or corresponding graph B is called in accordance with an opcode which is decoded by 0501 .

Fig. 5b schematically the figure on the individual cells, said pipelined arithmetic logic unit Character is symbolized in 0502nd

While larger memories for temporarily storing the data are preferably inserted in the reconfiguration points of FIG. 4, a simple synchronization of the data in the reconfiguration points of FIG. 5 is sufficient, since the data stream preferably runs as a whole through graph B and graph B does not continue is partitioned; this means that there is no need to cache the data.

Various loops are shown in FIG. 6a. Basically, loops can be handled in three ways:

• 1. Hardware approach: Loops are completely rolled out onto the target hardware ( 0601 a / b). As already explained, this is only possible with a few types of loops.
• 2. Data flow approach: Loops are set up across several cells within the data flow ( 0602 a / b). The end of the loop is fed back to the beginning of the loop.
• 3. Sequencer approach: A sequencer with a minimal instruction set executes the loop ( 0603 a / b). The cells of the target building blocks are designed in such a way that they contain the corresponding sequencer (cf. FIGS. 11a / b).

A suitable disassembly of loops can optimize their execution if necessary:

• 1. Using optimization methods according to the prior art, the loop body, that is to say the part to be repeated, can often be optimized by removing certain operations from the loop and placing them in front of or behind the loop ( 0604 a / b). This significantly reduces the number of commands to be sequenced. The removed operations are performed only once before or after the loop is executed.
• 2. Another optimization option is the division of loops into several smaller or shorter loops. The division takes place in such a way that several parallel or several sequential ( 0605 a / b) loops are created.

Fig. 7 illustrates the implementation of a recursion. The same resources ( 0701 ) in the form of cells are used for each recursion level ( 1-3 ). The results of each recursion level ( 1-3 ) are written to a memory ( 0702 ) built up according to the stack principle during construction ( 0711 ). The stack is dismantled simultaneously with the dismantling ( 0712 ) of the levels.

High-level language examples

For example, a module can be declared as follows:

module marks the beginning of a module.
input / output defines the input / output variables with the types ty _n .
begin. . . end mark the fuselage of the module.
register <regname1 / 2 <transfers the result to the output, whereby the result is buffered in the register specified by <regname1 / 2 <. <regname1 / 2 <is a global reference to a specific register.

The following storage types are available as additional transfer modes to the output:
fifo <fifoname <, whereby the data is transferred to a memory that works according to the FIFO principle. fifoname eats a global reference to a specific memory operating in FIFO mode. terminate @ is the parameter or the signal. "fifofull" expanded, indicating that the memory is full.
stack <stackname <, whereby the data is transferred to a memory that works according to the stack principle. stackname is a global reference to a specific memory working in stack mode.
terminate @ distinguishes programming according to the method according to the invention from conventional sequential programming. The command defines the termination criterion of the module. The result variables res1 and res2 are not evaluated by terminate @ with their actual value; instead, only the validity of the variables (i.e. their status signal) is checked. If both variables are valid, the module terminates with the value 1. This means that a signal with the value 1 is forwarded to the higher-level loading unit, whereupon the higher-level loading unit loads the subsequent module.

In this example, register is defined using input data. Where <regname1 <is the same as in example1. This causes the register that takes the output data in example1 to provide the input data for example2.
fifo defines a FIFO memory with a depth of 256 for the output data res1. The full flag (fifofull) of the FIFO memory is used in terminate @ as an abort criterion.

define defines an interface for data (register, memory, etc.). The required resources and the name of the interface are specified in the definition. Since the resources are clearly stated and can only be used once, the definition is global, ie the designation applies to the entire program.
call calls a module as a subroutine.
signal defines a signal as an output signal without using buffering.

The module main is terminated by terminate @ (example2), as soon as the subroutine example2 terminates.

Through the global declaration "define..." In principle, it is no longer necessary to include the input / output signals defined in this way in the interface declaration of the modules. The corresponding modified example modules would then look like this:

. . .

The status information of the processor model

To determine the states within a graph, the status registers of the individual cells (PAEs) are made available to all other arithmetic units via a status bus system ( 0802 ) that exists in addition to the data bus ( 0801 ) ( FIG. 8b). This means that one cell (PAE X) can evaluate the status information of another cell (PAE Y) and processes the data accordingly. In order to clarify the difference to existing parallel computer systems, the state of the art is given in FIG. 8a. A multiprocessor system is shown, the processors of which are connected to one another via a common data bus ( 0803 ). There is no explicit bus system for the synchronous exchange of data and status.

Finally, it should be noted that depending on the task, both the data flow graph and the control flow graph correspond can be treated according to the described method.

Hardware extensions compared to PACT02 and PACT04

With PACT02 and PACT04, the state of the art is related to aµf defines the configuration properties of cells (PAEs) and published in DE 196 51 075 (PACT02) and in DE 196 54 846 (PACT04).

Two properties are to be considered:

• 1. According to PACT02, a PAE is assigned a set of configuration registers which contains a configuration ( FIG. 8a).
• 2. According to PACT04, a group of PAEs can access a memory for storing or reading data ( FIG. 8b).

The task is,

• a) to create a process that the reconfiguration of. PAEs accelerated and timed by the higher-level loading unit decoupled, and  
• b) to interpret the procedure so that the Possibility is created over several configurations Sequences.

Decoupling of the configuration register

The configuration register is decoupled from the higher-level loading unit (CT) ( FIG. 9) by using a set of several configuration registers ( 0901 ). Exactly one of the configuration registers selectively determines the function of the PAE. The active register is selected using a multiplexer ( 0902 ). The CT can write to any of the configuration registers as long as this does not determine the current configuration of the PAE. Which configuration register is selected by 0902 can be determined by different sources:

• 1. An arbitrary status signal or a group of arbitrary status signals which are routed to 0902 via a bus system ( 0802 ) ( FIG. 9a). The status signals are generated by any PAEs or made available by external connections of the block (see Fig. 8).
• 2. The status signal of the PAE, which is configured by 0901/0902, is used for selection (Fig. 9b).
• 3. A signal generated by the higher-level CT is used for selection ( FIG. 9c).

It is possible to save the incoming signals ( 0903 , 0904 , 0905 ) for a certain period of time using a register.

By using several registers, the CT is timed decoupled. This means that the CT can have several configurations "preload" without any direct time dependency consists.  

Only the selected register in 0901 has not yet been loaded, the configuration of the PAE is waited until the CT has loaded the register. In order to determine whether a register has valid information, a "valid bit" ( 0906 ) can be inserted per register, which is set by the CT. If 0906 is not set for a selected register, the CT prompts you to set the register as quickly as possible.

The method described in FIG. 9 can easily be expanded to a sequencer ( FIG. 10). For this purpose, a microcontroller ( 1001 ) is used to control the selection signals of the multiplexer ( 0902 ). The sequencer determined dependent on the currently selected configuration (1002) and an additional status information (1003/1004), the next to be selected configuration. The status information

• a) the status of the status signal of the PAE, which is configured by 0901/0902 (FIG. 10a).
• b) be any status signal supplied via 0802 ( FIG. 10b).
• c) a combination of (a) and (b).

For easy understanding, 0901 can be viewed as a memory, with 0902 addressing a command from 1001 . The addressing depends on the command itself and on a status register. In this respect, the construction of a "von Neumann" machine corresponds, with the difference that

• a) universal usability, i.e. not to use the sequencer (cf. Fig. 9)
• b) that the status signal does not have to be generated by the arithmetic unit assigned to the sequencer (PAE), but can come from any other arithmetic unit (cf. FIG. 10b).

It is important that the sequencer can make jumps, especially conditional jumps, within 0901 .

Another additional or alternative method ( FIG. 11) for setting up sequencers within the above-mentioned modules is the use of the internal data memory ( 1101 ) for storing the configuration information for a PAE. The data output of a memory is switched to a configuration input of a PAE ( 1102 ). The address ( 1103 ) for 1101 can be generated by the same PAE or any other.

The sequencer is not fixed in this method implemented but is by a PAE or a group modeled by PAEs.

Claims (2)

1. Method for executing programs on a block with a one- or multi-dimensional cell structure, characterized in that data flow or control flow graphs are partitioned into temporally separate subgraphs and sequentially mapped and executed on the block. 2. Hardware with decoupled configuration register.