US20050080962A1 - Hardware management of JAVA threads - Google Patents

Hardware management of JAVA threads Download PDF

Info

Publication number
US20050080962A1
US20050080962A1 US10/335,332 US33533202A US2005080962A1 US 20050080962 A1 US20050080962 A1 US 20050080962A1 US 33533202 A US33533202 A US 33533202A US 2005080962 A1 US2005080962 A1 US 2005080962A1
Authority
US
United States
Prior art keywords
computing system
threads
control processor
thread
thread control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/335,332
Other versions
US7089340B2 (en
Inventor
Vladimir Penkovski
Hsien-Cheng Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US10/335,332 priority Critical patent/US7089340B2/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, HSIEN-CHENG E., PENKOVSKI, VLADIMIR M.
Publication of US20050080962A1 publication Critical patent/US20050080962A1/en
Application granted granted Critical
Publication of US7089340B2 publication Critical patent/US7089340B2/en
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526Mutual exclusion algorithms
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/52Indexing scheme relating to G06F9/52
    • G06F2209/522Manager

Definitions

  • Embodiments of the invention relate to a system for managing threads.
  • a “thread” is generally defined as a sequence of instructions that, when executed, perform a task. Multiple threads may be processed concurrently to perform different tasks such as those tasks necessary to collectively handle a transaction request.
  • a “transaction request” is a message transmitted over a network that indicates what kind of service is requested. For instance, the message may request to browse some data contained in a database. In order to service the request, the recipient initiates a particular task that corresponds to the nature of the requested task.
  • thread management involves management of queues, synchronizing, waking up and putting-to-sleep threads, context switches and many other known functions. For instance, in systems with a very high thread count, on the order of thousands for example, operations of the systems can be bogged down simply due to thread management and overhead, namely the time it takes to process threads.
  • a proposed solution of reducing the high processing demands is to preclude the use of a large number of threads to handle transaction requests. Rather, single threads or a few threads may be configured to handle such requests. This leads to poor system scalability.
  • FIG. 1 is a first exemplary diagram of a computing system featuring a thread control processor (TCP);
  • TCP thread control processor
  • FIG. 2 is a second exemplary diagram of a computing system featuring the TCP.
  • FIG. 3 is an exemplary block diagram illustrating operations of the TCP.
  • Certain embodiments of the invention relate to a computing system, co-processor and method for managing threads.
  • thread management overhead is off-loaded to specialized hardware implemented in circuitry proximate to a system processor.
  • thread management is integrated into the system processor.
  • a “computing system” may generally be considered as hardware, software, firmware or any combination thereof that is configured to process transaction requests.
  • Some illustrative examples of a computing system include a server (e.g., web server or application server), a set-top box and the like.
  • a “thread” is a sequence instructions that, when executed, perform one or more functions or tasks.
  • the threads may be stored in a processor-readable medium, which is any medium that can store or transfer information.
  • processor-readable medium include, but are not limited or restricted to a programmable electronic circuit, a semiconductor memory device, a volatile memory (e.g., random access memory, etc.), a non-volatile memory (e.g., read-only memory, flash memory, etc.), a floppy diskette, an optical disk such as a compact disk (CD) or digital versatile disc (DVD), a hard drive disk, or any type of communication link.
  • the computing system 100 comprises a processor unit 110 , a thread control processor (TCP) 120 , a system memory 130 , synchronization primitives 140 and one or more I/O subsystems 150 .
  • TCP thread control processor
  • processor unit 110 comprises one or more (M) processors 112 1 - 112 M .
  • the particular number “M” of processors forming processor unit 110 is optimized on the basis cost versus performance. For simplicity in the present description, two processors 112 1 and 112 M are illustrated.
  • An operating system (O/S) 114 is accessible to processors 112 1 and 112 M and uses a driver 116 to communicate with TCP 120 .
  • processors represents a central processing unit (CPU) of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture.
  • CISC complex instruction set computers
  • RISC reduced instruction set computers
  • VLIW very long instruction word
  • a processor may be implemented as an application specific integrated circuit (ASIC), a digital signal processor, a state machine, or the like.
  • processor unit 110 is in communication with TCP 120 .
  • TCP 120 may be implemented as (i) a co-processor (as shown) separately positioned on a circuit board featuring processor unit 110 or (ii) additional circuitry implemented either on the same integrated circuit chip of a processor (e.g., processor 112 1 ) or on a separate integrated circuit chip within the same processor package (see FIG. 2 ).
  • TCP 120 is responsible for maintaining threads (e.g., JAVA® threads) operating within the computing system 100 . For instance, TCP 120 performs wake-up and put-to-sleep, thread scheduling, event notification and other miscellaneous tasks such as queue management, priority computation and other like functions. Interconnects 160 and 170 are provided from the TCP 120 to synchronization primitives 140 and I/O subsystems 150 , respectively.
  • threads e.g., JAVA® threads
  • Interconnects 160 and 170 are provided from the TCP 120 to synchronization primitives 140 and I/O subsystems 150 , respectively.
  • I/O subsystems 150 comprise networking network interface controllers (NICs) 152 and disk controllers 154 . These I/O devices may be configured to communicate with TCP 120 .
  • NICs networking network interface controllers
  • disk controllers 154 disk controllers 154 .
  • synchronization primitives 140 include a mutual exclusion object (Mutex) 142 and/or a Semaphore 144 . Both of these primitives are responsible for coordinating the usage of shared resources such as files stored in system memory 130 or operating system (OS) routines.
  • Mutex mutual exclusion object
  • Semaphore 144 Semaphore
  • Mutex 142 is a program object created to enable the sharing of the same resource by multiple threads. Typically, when a multi-threaded program is commenced, it creates a mutex for each selected resource. Thereafter, when a thread accesses a resource, a corresponding mutex is configured to indicate that the resource is unavailable. Once the thread has concluded its use of the resource, the mutex is unlocked to allow another thread access to the resource.
  • Semaphore 144 is a variable with a value that indicates the status of a shared operating system (OS) resource. Hence, Semaphore 144 is normally located in designated place in operating system (or kernel) storage.
  • OS operating system
  • the TCP 120 manages all active threads in the computing system 100 .
  • eight (8) threads 200 , 210 , 220 , 230 , 240 , 250 , 260 and 270 are illustrated.
  • threads may be utilized.
  • the threads may be in either a RUN state, a WAIT state or a SLEEP state.
  • threads existing in a RUN state and loaded in processor unit 110 include threads 200 and 210 .
  • the TCP 120 supports automatic event notification, which allows signals to notify the TCP 120 about I/O events such as completion of a file read operation, completion of transmission of a message over a network via NIC and the like.
  • threads 240 , 250 and 260 may also exist in a WAIT state by waiting on synchronization primitives such as Mutex 142 1 , Mutex 142 2 and/or Semaphore 144 1 .
  • a thread such as thread 270 may simply be in a SLEEP state.
  • any thread 280 is placed in a RUN state when one of a number of conditions is satisfied. For instance, a thread 280 is ready-to-run when an I/O event that the thread is waiting on is completed. Alternatively, a thread 280 is ready-to-run when a synchronization primitive 140 that the thread 280 is waiting on is triggered. Yet another example is that a thread 280 is ready-to-run when it is awoken from a SLEEP state.
  • the TCP 120 selects threads in a RUN state (i.e., ready-to-run threads) and provides them to one of the available processor 112 1 - 112 M in the processor unit 110 for execution.
  • a priority-based scheduler (not shown) can be used to select one of the threads based on the chosen priority rules.
  • Other scheduling algorithms such as the well-known round-robin technique can be used. Threads are placed into a SLEEP state when either time quanta expires or threads request an I/O operation from an I/O device.
  • TCP 120 can support multiple threading models.
  • JAVA® Threads or native operating system threads operate in accordance with embodiments of the invention.
  • JAVA® threads are one preferred target for the TCP 120 because of their widespread use in current systems.
  • the TCP 120 may reside on a circuit board.
  • the separate processor can use older technology and support a high number of threads.
  • thread management hardware can be coupled directly to each of the I/O subsystems 150 and enable automatic event notification to threads such as completion of a file read operation.
  • traditional threading control hardware deals with threading control only.

Abstract

A system for managing threads to handle transaction requests connected to input/output (I/O) subsystems to enable notification to threads to complete operations.

Description

    1. FIELD OF THE INVENTION
  • Embodiments of the invention relate to a system for managing threads.
  • 2. GENERAL BACKGROUND
  • In computing systems, such as web servers or application servers, threads are used to handle transaction requests. A “thread” is generally defined as a sequence of instructions that, when executed, perform a task. Multiple threads may be processed concurrently to perform different tasks such as those tasks necessary to collectively handle a transaction request. A “transaction request” is a message transmitted over a network that indicates what kind of service is requested. For instance, the message may request to browse some data contained in a database. In order to service the request, the recipient initiates a particular task that corresponds to the nature of the requested task.
  • One problem associated with conventional computing systems is that a significant amount of processing time is spent by a central processing unit (CPU) on thread management. In general, “thread management” involves management of queues, synchronizing, waking up and putting-to-sleep threads, context switches and many other known functions. For instance, in systems with a very high thread count, on the order of thousands for example, operations of the systems can be bogged down simply due to thread management and overhead, namely the time it takes to process threads.
  • A proposed solution of reducing the high processing demands is to preclude the use of a large number of threads to handle transaction requests. Rather, single threads or a few threads may be configured to handle such requests. This leads to poor system scalability.
  • Currently, there are computing systems that have threading control built into the CPU such as a CRAY® MTA™ computer. However, these systems suffer from a number of disadvantages. First, only a maximum of 128 threads are supported per CPU. As a result, support of a larger thread count would need to be implemented in software. Second, integrating circuitry to support up to 128 threads occupies a significant amount of silicon real estate, and thereby, increases the overall costs for the CPU. Third, the threading control hardware of conventional computing systems is stand-alone and is not connected to the rest of the system (e.g., input/output “I/O” circuitry). Since this hardware does not have the proper interface with the rest of the system, true automatic thread management is not provided (e.g., waking up a thread when a “file read” operation that the thread has been waiting on is completed).
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention.
  • FIG. 1 is a first exemplary diagram of a computing system featuring a thread control processor (TCP);
  • FIG. 2 is a second exemplary diagram of a computing system featuring the TCP; and
  • FIG. 3 is an exemplary block diagram illustrating operations of the TCP.
  • DETAILED DESCRIPTION
  • Certain embodiments of the invention relate to a computing system, co-processor and method for managing threads. For one embodiment of the invention, thread management overhead is off-loaded to specialized hardware implemented in circuitry proximate to a system processor. In another embodiment of the invention, thread management is integrated into the system processor.
  • Certain details are set forth below in order to provide a thorough understanding of various embodiments of the invention, albeit the invention may be practiced through many embodiments other that those illustrated. Well-known circuitry and operations are not set forth in detail in order to avoid unnecessarily obscuring this description.
  • Herein, a “computing system” may generally be considered as hardware, software, firmware or any combination thereof that is configured to process transaction requests. Some illustrative examples of a computing system include a server (e.g., web server or application server), a set-top box and the like.
  • A “thread” is a sequence instructions that, when executed, perform one or more functions or tasks. The threads may be stored in a processor-readable medium, which is any medium that can store or transfer information. Examples of “processor-readable medium” include, but are not limited or restricted to a programmable electronic circuit, a semiconductor memory device, a volatile memory (e.g., random access memory, etc.), a non-volatile memory (e.g., read-only memory, flash memory, etc.), a floppy diskette, an optical disk such as a compact disk (CD) or digital versatile disc (DVD), a hard drive disk, or any type of communication link.
  • Referring to FIG. 1, an exemplary diagram of a computing system 100 is shown. The computing system 100 comprises a processor unit 110, a thread control processor (TCP) 120, a system memory 130, synchronization primitives 140 and one or more I/O subsystems 150.
  • As shown in this embodiment of the invention, processor unit 110 comprises one or more (M) processors 112 1-112 M. The particular number “M” of processors forming processor unit 110 is optimized on the basis cost versus performance. For simplicity in the present description, two processors 112 1 and 112 M are illustrated. An operating system (O/S) 114 is accessible to processors 112 1 and 112 M and uses a driver 116 to communicate with TCP 120.
  • Each “processor” represents a central processing unit (CPU) of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. Of course, a processor may be implemented as an application specific integrated circuit (ASIC), a digital signal processor, a state machine, or the like.
  • As shown in FIG. 1, processor unit 110 is in communication with TCP 120. TCP 120 may be implemented as (i) a co-processor (as shown) separately positioned on a circuit board featuring processor unit 110 or (ii) additional circuitry implemented either on the same integrated circuit chip of a processor (e.g., processor 112 1) or on a separate integrated circuit chip within the same processor package (see FIG. 2).
  • TCP 120 is responsible for maintaining threads (e.g., JAVA® threads) operating within the computing system 100. For instance, TCP 120 performs wake-up and put-to-sleep, thread scheduling, event notification and other miscellaneous tasks such as queue management, priority computation and other like functions. Interconnects 160 and 170 are provided from the TCP 120 to synchronization primitives 140 and I/O subsystems 150, respectively.
  • For this embodiment of the invention, I/O subsystems 150 comprise networking network interface controllers (NICs) 152 and disk controllers 154. These I/O devices may be configured to communicate with TCP 120.
  • Herein, embodied in hardware or software, synchronization primitives 140 include a mutual exclusion object (Mutex) 142 and/or a Semaphore 144. Both of these primitives are responsible for coordinating the usage of shared resources such as files stored in system memory 130 or operating system (OS) routines.
  • In general, Mutex 142 is a program object created to enable the sharing of the same resource by multiple threads. Typically, when a multi-threaded program is commenced, it creates a mutex for each selected resource. Thereafter, when a thread accesses a resource, a corresponding mutex is configured to indicate that the resource is unavailable. Once the thread has concluded its use of the resource, the mutex is unlocked to allow another thread access to the resource.
  • Similar in purpose to Mutex 142, Semaphore 144 is a variable with a value that indicates the status of a shared operating system (OS) resource. Hence, Semaphore 144 is normally located in designated place in operating system (or kernel) storage.
  • Referring now to FIG. 3, an exemplary block diagram illustrating operations of the TCP 120 is shown. The TCP 120 manages all active threads in the computing system 100. For simplicity in illustration, eight (8) threads 200, 210, 220, 230, 240, 250, 260 and 270 (generally referred to as “thread(s) 280”) are illustrated.
  • In practice, however, thousands of threads may be utilized. The threads may be in either a RUN state, a WAIT state or a SLEEP state. For instance, threads existing in a RUN state and loaded in processor unit 110 include threads 200 and 210.
  • Other threads may be existing in a WAIT state such as threads 220 and 230 waiting on an I/O event within any of the I/O subsystems 150. Hence, the TCP 120 supports automatic event notification, which allows signals to notify the TCP 120 about I/O events such as completion of a file read operation, completion of transmission of a message over a network via NIC and the like.
  • Also, threads 240, 250 and 260 may also exist in a WAIT state by waiting on synchronization primitives such as Mutex 142 1, Mutex 142 2 and/or Semaphore 144 1. Alternatively, a thread such as thread 270 may simply be in a SLEEP state.
  • As indicated upon, any thread 280 is placed in a RUN state when one of a number of conditions is satisfied. For instance, a thread 280 is ready-to-run when an I/O event that the thread is waiting on is completed. Alternatively, a thread 280 is ready-to-run when a synchronization primitive 140 that the thread 280 is waiting on is triggered. Yet another example is that a thread 280 is ready-to-run when it is awoken from a SLEEP state. The TCP 120 selects threads in a RUN state (i.e., ready-to-run threads) and provides them to one of the available processor 112 1-112 M in the processor unit 110 for execution.
  • In case of multiple threads in a RUN state being available, a priority-based scheduler (not shown) can be used to select one of the threads based on the chosen priority rules. Other scheduling algorithms such as the well-known round-robin technique can be used. Threads are placed into a SLEEP state when either time quanta expires or threads request an I/O operation from an I/O device.
  • In general, TCP 120 can support multiple threading models. For example, JAVA® Threads or native operating system threads operate in accordance with embodiments of the invention. However, JAVA® threads are one preferred target for the TCP 120 because of their widespread use in current systems.
  • In an embodiment where the TCP 120 is a separate co-processor, the TCP 120 may reside on a circuit board. Lower cost is enabled since the separate processor can use older technology and support a high number of threads. Thus, for the embodiment of FIG. 1, thread management hardware can be coupled directly to each of the I/O subsystems 150 and enable automatic event notification to threads such as completion of a file read operation. In contrast, traditional threading control hardware deals with threading control only.
  • While the invention has been described in terms of various embodiments, the invention should not limited to only those embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims (19)

1. A computing system comprising:
a processing unit; and
a thread control processor coupled to the processing unit, the thread control processor to exclusively manage a plurality of active threads and to communicate with synchronization primitives for coordinating usage of shared resources by at least one of the plurality of active threads.
2. The computing system of claim 1, wherein one of the synchronization primitives includes a mutual exclusion object (Mutex).
3. The computing system of claim 1, wherein one of the synchronization primitives includes a Semaphore residing in storage of an operating system processed by the processing unit.
4. The computing system of claim 1, wherein the thread control processor is a co-processor.
5. The computing system of claim 1, wherein the plurality of threads supported by the thread control processor comprises at least one thread in a RUN state loaded into the processing unit.
6. The computing system of claim 5, wherein the plurality of threads supported by the thread control processor further comprises at least one thread in a WAIT state by awaiting a response one of the synchronization primitives that another thread has completed use of a shared resource.
7. The computing system of claim 6, wherein the shared resource is one of a file stored in a system memory and a operating system routine.
8. The computing system of claim 1 further comprising an input/output (I/O) device coupled to the thread control processor, the thread control processor being adapted to receive a signal to indicate completion of an I/O event form the I/O device.
9. The computing system of claim 8, wherein the I/O device is a disk controller and the I/O event is a completion of a file read operation.
10. The computing system of claim 8, wherein the I/O device is a network interface controller and the I/O event is a transmission of a message onto a network via the network interface controller.
11. A computing system comprising:
a memory to contain a synchronization primitive;
an input/output (I/O) subsystem including at least one I/O device;
a processing unit to process a control thread; and
a thread control processor coupled to the processing unit, the thread control processor to exclusively manage a plurality of active threads and to communicate with (i) the synchronization primitive via a first interconnect for coordinating usage of a shared resource by the plurality of active threads and (ii) the I/O device via a second interconnect to receive information when an I/O event by the I/O device has completed.
12. The computing system of claim 11, wherein the synchronization primitive comprises one of a mutual exclusion object (Mutex) and a Semaphore residing in the memory.
13. The computing system of claim 11, wherein the I/O device is a disk controller.
14. The computing system of claim 13, wherein the I/O event is a file read operation being completed.
15. The computing system of claim 11, wherein the I/O device is a network interface controller.
16. The computing system of claim 11, wherein the I/O event is a transmission of a message onto a network via the network interface controller.
17. A method comprising:
implementing specialized hardware in a computing system including a thread control processor;
interconnecting the thread control processor to an input/output (I/O) device and to a system memory loaded with at least one synchronization primitive;
exclusively managing a plurality of active threads by the thread control processor of the computing system.
18. The method of claim 17, wherein the exclusive managing of the plurality of active threads comprises maintaining threads until they become ready-to-run and connecting threads for operation when ready-to-run.
19. The method of claim 18, wherein the exclusive managing of the plurality of active threads further comprises selecting ready-to-run threads and connecting them to available processing resources.
US10/335,332 2002-12-31 2002-12-31 Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives Expired - Fee Related US7089340B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/335,332 US7089340B2 (en) 2002-12-31 2002-12-31 Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/335,332 US7089340B2 (en) 2002-12-31 2002-12-31 Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives

Publications (2)

Publication Number Publication Date
US20050080962A1 true US20050080962A1 (en) 2005-04-14
US7089340B2 US7089340B2 (en) 2006-08-08

Family

ID=34421385

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/335,332 Expired - Fee Related US7089340B2 (en) 2002-12-31 2002-12-31 Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives

Country Status (1)

Country Link
US (1) US7089340B2 (en)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040003018A1 (en) * 2002-06-26 2004-01-01 Pentkovski Vladimir M. Method and system for efficient handlings of serial and parallel java operations
US20070150895A1 (en) * 2005-12-06 2007-06-28 Kurland Aaron S Methods and apparatus for multi-core processing with dedicated thread management
US20090199030A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Hardware Wake-and-Go Mechanism for a Data Processing System
US20090199029A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Wake-and-Go Mechanism with Data Monitoring
US20090199197A1 (en) * 2008-02-01 2009-08-06 International Business Machines Corporation Wake-and-Go Mechanism with Dynamic Allocation in Hardware Private Array
US20090199184A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Wake-and-Go Mechanism With Software Save of Thread State
US20100268791A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Programming Idiom Accelerator for Remote Update
US20100268790A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Complex Remote Update Programming Idiom Accelerator
US20100269115A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Managing Threads in a Wake-and-Go Engine
US20100293340A1 (en) * 2008-02-01 2010-11-18 Arimilli Ravi K Wake-and-Go Mechanism with System Bus Response
US20100293341A1 (en) * 2008-02-01 2010-11-18 Arimilli Ravi K Wake-and-Go Mechanism with Exclusive System Bus Response
US20110173423A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Look-Ahead Hardware Wake-and-Go Mechanism
US20110173419A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Look-Ahead Wake-and-Go Engine With Speculative Execution
US20110173417A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Programming Idiom Accelerators
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8880853B2 (en) 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8886919B2 (en) 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4529063B2 (en) * 2001-03-30 2010-08-25 ルネサスエレクトロニクス株式会社 System simulator, simulation method, and simulation program
US7496921B2 (en) * 2003-08-29 2009-02-24 Intel Corporation Processing block with integrated light weight multi-threading support
US8230440B2 (en) * 2009-03-06 2012-07-24 International Business Machines Corporation System and method to distribute accumulated processor utilization charges among multiple threads
US9542236B2 (en) 2011-12-29 2017-01-10 Oracle International Corporation Efficiency sequencer for multiple concurrently-executing threads of execution
US9514069B1 (en) 2012-05-24 2016-12-06 Schwegman, Lundberg & Woessner, P.A. Enhanced computer processor and memory management architecture
US10430234B2 (en) 2016-02-16 2019-10-01 Red Hat, Inc. Thread coordination in a rule engine using a state machine
US11550642B1 (en) 2021-08-18 2023-01-10 Micron Technology, Inc. Mechanism to trigger early termination of cooperating processes

Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828880A (en) * 1995-07-06 1998-10-27 Sun Microsystems, Inc. Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datum
US6044403A (en) * 1997-12-31 2000-03-28 At&T Corp Network server platform for internet, JAVA server and video application server
US6141794A (en) * 1998-10-16 2000-10-31 Sun Microsystems, Inc. System and method for synchronizing access to shared variables in a virtual machine in a digital computer system
US6158048A (en) * 1998-05-29 2000-12-05 Intel Corporation Method for eliminating common subexpressions from java byte codes
US6167253A (en) * 1995-01-12 2000-12-26 Bell Atlantic Network Services, Inc. Mobile data/message/electronic mail download system utilizing network-centric protocol such as Java
US6170015B1 (en) * 1998-05-15 2001-01-02 Nortel Networks Limited Network apparatus with Java co-processor
US6230311B1 (en) * 1998-06-12 2001-05-08 International Business Machines Corporation Apparatus and method for disabling methods called on an object
US6247025B1 (en) * 1997-07-17 2001-06-12 International Business Machines Corporation Locking and unlocking mechanism for controlling concurrent access to objects
US6249288B1 (en) * 1998-12-14 2001-06-19 Ati International Srl Multi thread display controller
US6272674B1 (en) * 1998-12-14 2001-08-07 Nortel Networks Limited Method and apparatus for loading a Java application program
US6289395B1 (en) * 1997-11-24 2001-09-11 International Business Machines Corporation Generic Java-based event processor for scripting Java beans
US6292935B1 (en) * 1998-05-29 2001-09-18 Intel Corporation Method for fast translation of java byte codes into efficient native processor code
US6324688B1 (en) * 1998-07-30 2001-11-27 International Business Machines Corporation Method and apparatus for optimizing execution of Java programs
US6327609B1 (en) * 1999-09-22 2001-12-04 Audiobase, Inc. System and method for using cookies in java
US6332215B1 (en) * 1998-12-08 2001-12-18 Nazomi Communications, Inc. Java virtual machine hardware for RISC and CISC processors
US6401134B1 (en) * 1997-07-25 2002-06-04 Sun Microsystems, Inc. Detachable java applets
US6427153B2 (en) * 1998-12-04 2002-07-30 Sun Microsystems, Inc. System and method for implementing Java-based software network management objects
US6430564B1 (en) * 1999-03-01 2002-08-06 Hewlett-Packard Company Java data manager for embedded device
US6430568B1 (en) * 1998-07-22 2002-08-06 Hewlett-Packard Company Methods and systems for java inter-applet communication
US6430570B1 (en) * 1999-03-01 2002-08-06 Hewlett-Packard Company Java application manager for embedded device
US6433794B1 (en) * 1998-07-31 2002-08-13 International Business Machines Corporation Method and apparatus for selecting a java virtual machine for use with a browser
US6481006B1 (en) * 1999-05-06 2002-11-12 International Business Machines Corporation Method and apparatus for efficient invocation of Java methods from native codes
US6507946B2 (en) * 1999-06-11 2003-01-14 International Business Machines Corporation Process and system for Java virtual method invocation
US6513158B1 (en) * 1999-11-15 2003-01-28 Espial Group Inc. Method and apparatus for running multiple java applications simultaneously
US20030041173A1 (en) * 2001-08-10 2003-02-27 Hoyle Stephen L. Synchronization objects for multi-computer systems
US6567084B1 (en) * 2000-07-27 2003-05-20 Ati International Srl Lighting effect computation circuit and method therefore
US20040003018A1 (en) * 2002-06-26 2004-01-01 Pentkovski Vladimir M. Method and system for efficient handlings of serial and parallel java operations
US6751389B2 (en) * 1998-09-21 2004-06-15 Pirelli Cavi E Sistemi S.P.A. Optical fiber for extended wavelength band
US6826749B2 (en) * 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6895575B2 (en) * 2001-06-20 2005-05-17 Sap Ag Generic Java rule engine framework

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10333925A (en) * 1997-02-27 1998-12-18 Zuno Ltd Autonomous agent architecture
US6571389B1 (en) 1999-04-27 2003-05-27 International Business Machines Corporation System and method for improving the manageability and usability of a Java environment

Patent Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167253A (en) * 1995-01-12 2000-12-26 Bell Atlantic Network Services, Inc. Mobile data/message/electronic mail download system utilizing network-centric protocol such as Java
US5828880A (en) * 1995-07-06 1998-10-27 Sun Microsystems, Inc. Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datum
US6247025B1 (en) * 1997-07-17 2001-06-12 International Business Machines Corporation Locking and unlocking mechanism for controlling concurrent access to objects
US6401134B1 (en) * 1997-07-25 2002-06-04 Sun Microsystems, Inc. Detachable java applets
US6289395B1 (en) * 1997-11-24 2001-09-11 International Business Machines Corporation Generic Java-based event processor for scripting Java beans
US6044403A (en) * 1997-12-31 2000-03-28 At&T Corp Network server platform for internet, JAVA server and video application server
US6170015B1 (en) * 1998-05-15 2001-01-02 Nortel Networks Limited Network apparatus with Java co-processor
US6292935B1 (en) * 1998-05-29 2001-09-18 Intel Corporation Method for fast translation of java byte codes into efficient native processor code
US6158048A (en) * 1998-05-29 2000-12-05 Intel Corporation Method for eliminating common subexpressions from java byte codes
US6230311B1 (en) * 1998-06-12 2001-05-08 International Business Machines Corporation Apparatus and method for disabling methods called on an object
US6430568B1 (en) * 1998-07-22 2002-08-06 Hewlett-Packard Company Methods and systems for java inter-applet communication
US6324688B1 (en) * 1998-07-30 2001-11-27 International Business Machines Corporation Method and apparatus for optimizing execution of Java programs
US6433794B1 (en) * 1998-07-31 2002-08-13 International Business Machines Corporation Method and apparatus for selecting a java virtual machine for use with a browser
US6751389B2 (en) * 1998-09-21 2004-06-15 Pirelli Cavi E Sistemi S.P.A. Optical fiber for extended wavelength band
US6141794A (en) * 1998-10-16 2000-10-31 Sun Microsystems, Inc. System and method for synchronizing access to shared variables in a virtual machine in a digital computer system
US6427153B2 (en) * 1998-12-04 2002-07-30 Sun Microsystems, Inc. System and method for implementing Java-based software network management objects
US6332215B1 (en) * 1998-12-08 2001-12-18 Nazomi Communications, Inc. Java virtual machine hardware for RISC and CISC processors
US6826749B2 (en) * 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6249288B1 (en) * 1998-12-14 2001-06-19 Ati International Srl Multi thread display controller
US6272674B1 (en) * 1998-12-14 2001-08-07 Nortel Networks Limited Method and apparatus for loading a Java application program
US6430570B1 (en) * 1999-03-01 2002-08-06 Hewlett-Packard Company Java application manager for embedded device
US6430564B1 (en) * 1999-03-01 2002-08-06 Hewlett-Packard Company Java data manager for embedded device
US6481006B1 (en) * 1999-05-06 2002-11-12 International Business Machines Corporation Method and apparatus for efficient invocation of Java methods from native codes
US6507946B2 (en) * 1999-06-11 2003-01-14 International Business Machines Corporation Process and system for Java virtual method invocation
US6327609B1 (en) * 1999-09-22 2001-12-04 Audiobase, Inc. System and method for using cookies in java
US6513158B1 (en) * 1999-11-15 2003-01-28 Espial Group Inc. Method and apparatus for running multiple java applications simultaneously
US6567084B1 (en) * 2000-07-27 2003-05-20 Ati International Srl Lighting effect computation circuit and method therefore
US6895575B2 (en) * 2001-06-20 2005-05-17 Sap Ag Generic Java rule engine framework
US20030041173A1 (en) * 2001-08-10 2003-02-27 Hoyle Stephen L. Synchronization objects for multi-computer systems
US20040003018A1 (en) * 2002-06-26 2004-01-01 Pentkovski Vladimir M. Method and system for efficient handlings of serial and parallel java operations

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040003018A1 (en) * 2002-06-26 2004-01-01 Pentkovski Vladimir M. Method and system for efficient handlings of serial and parallel java operations
US20070150895A1 (en) * 2005-12-06 2007-06-28 Kurland Aaron S Methods and apparatus for multi-core processing with dedicated thread management
US8145849B2 (en) 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US20090199184A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Wake-and-Go Mechanism With Software Save of Thread State
US20090199197A1 (en) * 2008-02-01 2009-08-06 International Business Machines Corporation Wake-and-Go Mechanism with Dynamic Allocation in Hardware Private Array
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US20090199030A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Hardware Wake-and-Go Mechanism for a Data Processing System
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8788795B2 (en) 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US20100293340A1 (en) * 2008-02-01 2010-11-18 Arimilli Ravi K Wake-and-Go Mechanism with System Bus Response
US20100293341A1 (en) * 2008-02-01 2010-11-18 Arimilli Ravi K Wake-and-Go Mechanism with Exclusive System Bus Response
US20110173423A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Look-Ahead Hardware Wake-and-Go Mechanism
US20110173419A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Look-Ahead Wake-and-Go Engine With Speculative Execution
US20110173417A1 (en) * 2008-02-01 2011-07-14 Arimilli Ravi K Programming Idiom Accelerators
US8015379B2 (en) 2008-02-01 2011-09-06 International Business Machines Corporation Wake-and-go mechanism with exclusive system bus response
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8880853B2 (en) 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US20090199029A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Wake-and-Go Mechanism with Data Monitoring
US8640142B2 (en) 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with dynamic allocation in hardware private array
US8640141B2 (en) 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US8250396B2 (en) 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8316218B2 (en) 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8386822B2 (en) 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8452947B2 (en) 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8612977B2 (en) 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8230201B2 (en) 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
US20100268790A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Complex Remote Update Programming Idiom Accelerator
US8145723B2 (en) 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8082315B2 (en) 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US20100269115A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Managing Threads in a Wake-and-Go Engine
US20100268791A1 (en) * 2009-04-16 2010-10-21 International Business Machines Corporation Programming Idiom Accelerator for Remote Update
US8886919B2 (en) 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources

Also Published As

Publication number Publication date
US7089340B2 (en) 2006-08-08

Similar Documents

Publication Publication Date Title
US7089340B2 (en) Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives
US10877766B2 (en) Embedded scheduling of hardware resources for hardware acceleration
KR102494804B1 (en) Data processing
US10733019B2 (en) Apparatus and method for data processing
US7370326B2 (en) Prerequisite-based scheduler
US8180973B1 (en) Servicing interrupts and scheduling code thread execution in a multi-CPU network file server
US7900210B2 (en) Application connector parallelism in enterprise application integration systems
US8171267B2 (en) Method and apparatus for migrating task in multi-processor system
JPH07101407B2 (en) Method and apparatus for scheduling
US11321123B2 (en) Determining an optimum number of threads to make available per core in a multi-core processor complex to executive tasks
US9529651B2 (en) Apparatus and method for executing agent
US20120297216A1 (en) Dynamically selecting active polling or timed waits
US20170220385A1 (en) Cross-platform workload processing
US20120102499A1 (en) OPTIMIZING THE PERFORMANCE OF HYBRID CPU SYSTEMS BASED UPON THE THREAD TYPE OF APPLICATIONS TO BE RUN ON THE CPUs
US20030110232A1 (en) Distributing messages between local queues representative of a common shared queue
US7765548B2 (en) System, method and medium for using and/or providing operating system information to acquire a hybrid user/operating system lock
AU603876B2 (en) Multiple i/o bus virtual broadcast of programmed i/o instructions
CN110532106A (en) The means of communication, device, equipment and storage medium between process
US8862786B2 (en) Program execution with improved power efficiency
CN117377943A (en) Memory-calculation integrated parallel processing system and method
JP7346649B2 (en) Synchronous control system and method
US20120158651A1 (en) Configuration of asynchronous message processing in dataflow networks
EP0264317B1 (en) Apparatus for the optimization of the performances of real-time primitives of a real-time executive kernel on multiprocessor architectures
US20230205580A1 (en) Dependency-aware server processing of dataflow applications
US8688880B2 (en) Centralized serialization of requests in a multiprocessor system

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PENKOVSKI, VLADIMIR M.;HSIEH, HSIEN-CHENG E.;REEL/FRAME:014001/0111

Effective date: 20021018

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20180808