WO1999018485A2 - Variable instruction set computer - Google Patents
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- WO1999018485A2 WO1999018485A2 PCT/IB1998/001453 IB9801453W WO9918485A2 WO 1999018485 A2 WO1999018485 A2 WO 1999018485A2 IB 9801453 W IB9801453 W IB 9801453W WO 9918485 A2 WO9918485 A2 WO 9918485A2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99951—File or database maintenance
- Y10S707/99952—Coherency, e.g. same view to multiple users
- Y10S707/99953—Recoverability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99951—File or database maintenance
- Y10S707/99956—File allocation
- Y10S707/99957—Garbage collection
Definitions
- the invention relates to a method for executing a source program on a processing unit comprising a predetermined microcontroller core for executing native instructions from a predetermined set of micro-controller specific instructions; the method comprising: a pre-processing step of expressing program statements of the source program in a sequence of instructions comprising virtual machine instructions: and storing the sequence of instructions in an instruction memory; and an execution step of fetching instructions from the instruction memory; using conversion means of the processing unit to convert virtual instructions fetched from the instruction memory into native instructions; and feeding the native instructions to the microcontroller core for execution
- the invention further relates to a processing unit for executing instructions of a virtual machine, the instructions being referred to as virtual machine instructions; the processing unit comprising: a predetermined microcontroller core for executing native instructions from a predetermined set of micro-controller specific instructions; the native instructions being different from the virtual machine instructions. an instruction memory for storing instructions including at least one of the virtual machine instructions; a converter comprising conversion means for converting a virtual machine instruction fetched from the instruction memory into at least one native instruction for execution by the microcontroller core.
- source programs are expressed in (compiled to) instructions of a virtual machine instead of native instructions of a microcontroller core on which the program is to be executed.
- a main reason for using a virtual machine is portability of programs between different machines (platforms).
- a program expressed in the virtual machine instructions of the virtual machine can be executed relatively easily on several concrete machines, using suitable interpreters operating on those machines.
- a driving force for using portable programs is Java, where Java programs are exchanged via Internet and can be executed on different native machines using processors with different instruction sets.
- Java programs are expressed in Java byte codes (JBCs), which form the instructions of the Java Virtual Machine. The resulting code is usually referred to as a Java applet.
- JBCs Java byte codes
- a hardware interpreter In itself a hardware interpreter is known in the form of a Prolog pre-processor for Warren's abstract instruction set. In the paper "A Prolog pre-processor for Warren's abstract instruction set" by B. Knodler and W. Rosenstiel. Microprocessing and Microprogramming 18 (1986) pages 71-81 , a preprocessor is described for interpreting programs written in the Prolog programming language on a Motorola 68000 processor (MC68000). A compiler is used to translate the Prolog source program into instructions, which have been defined by Mr. Warren and which are generally used for executing Prolog programs. The set of Warren instructions forms a virtual machine designed for executing Prolog programs.
- the sequence of Warren instructions resulting from the compilation are loaded into RAM and executed by the MC68000 with the aid of the pre-processor.
- the MC68000 After power-on, the MC68000 first performs a booting procedure by executing native MC68000 instructions. At the end of the booting procedure, the MC68000 is ready to initiate the execution of a Prolog program. This is started by jumping to a predetermined address range.
- the pre-processor is a memory-mapped device, which is mapped to this range. When the pre-processor is addressed it reads a Warren instruction (of the translated Prolog program) from its own RAM, adaptively synthesizes a sequence of MC68000 instructions and constants and sends these directly to the CPU for execution.
- the MC68000 instructions for each Warren instruction are stored in ROM of the pre-processor.
- the pre-processor translates one Warren instruction into a sequence of MC68000 instructions.
- the pre-processor contains its own RAM controller and ROM controller, which generate the addresses for the RAM and ROM of the pre-processor.
- the RAM controller manages the RAM instruction pointer.
- Each successive read operation of the MC68000 results in the pre-processor sending the next instruction (and optional constants) of the sequence to the CPU. If the sequence has been completed, a next read operation results in the first instruction of the sequence corresponding to the next Warren instruction of the program being send to the CPU.
- the known pre-processor supports one virtual machine (the Warren machine).
- the method is characterised in that the method comprises the steps of defining for the program statements of the source program a program-specific virtual machine with a corresponding set of virtual machine instructions, such that the expression of the program statements in the sequence of instructions requires less storage space in the instruction memory compared to using only native instructions for expressing the program statements: defining for the program-specific virtual machine an associated conversion means for converting virtual machine instructions of the program-specific virtual machine into native instructions of the microcontroller core; and representing the associated conversion means in the processing unit.
- a program-specific virtual machine is defined for a program such that the program can be expressed in a form which is more compact than if the program was expressed in native instructions of the core.
- an associated conversion means is defined.
- the conversion means may for instance be implemented using a conversion table or microcode stored in ROM or dedicated logic, such as a PLD.
- the defined conversion means is represented in the processing unit. In this way, fast execution of the program is maintained, whereas at the same time a compact representation is achieved.
- This method is particularly suitable for use with embedded applications.
- the source program relates to all program statements initially represented in the embedded system (for instance, the program present in the system when the user purchases the system) .
- the program may be stored in a permanent memory, such as ROM, or stored in a re-programmable memory, such as EEPROM.
- ROM read-only memory
- EEPROM erasable programmable memory
- processing units used for embedded applications are based on a family concept, where for a specific application a processing unit is created from a given microcontroller core and I/O or storage components required for the application. It is desired to make no or at least no significant modifications to the core or the components in order to reduce costs.
- virtual machine instructions are defined specifically for the program, giving full flexibility in achieving code compaction, whereas on the other hand an off-the-shelf core is used for executing the program.
- the required conversion from virtual machine instructions to native instructions is performed by a conversion means, which can be seen as a kind of pre-processor.
- Optimizing an ANSI C Interpreter with Superoperators Todd A. Proebsting, POPL'95:322-332, 1/95 describes the use of superoperators as an optimisation technique for bytecoded interpreters.
- a compiler is used to express the program in virtual machine instructions.
- the virtual machine instruction are chosen such that the representation of the program using the virtual machine instructions is more compact.
- An example of such a virtual machine is a stack machine, which is known for its compact representation.
- sequences of virtual machine instructions which occur frequently in the compiled code are identified and replaced by newly defined additional virtual machine instructions, where, for instance, one new instruction (a so-called superope- rator) replaces a sequence of four existing instructions.
- a superoperator can also be defined, by during the parsing phase of the compiler, identifying most frequently occurring terms in the expression tree which is built during an intermediate representation in the compiler. Only a limited number of superoperators are defined, e.g. , well less than 256. This allows a compact encoding of the superoperators (e.g. , using a single byte code). Part of the code range is then assigned for representing the original virtual machine instructions and part of the range is used for representing newly added virtual machine instructions representing the superoperators. By using only 20 superoperators already a significant code compaction can be achieved.
- the virtual machine instructions are interpreted using a software interpreter running on a MIPS R3000 or SPARC processor.
- a good level of code compaction can be achieved for different groups of program statements.
- program statements relating substantially to a same subset of native instructions are grouped together and a virtual machine is defined for such a group.
- a different virtual machine may be defined for integer operations than for floating point operations. It is preferred to group program statements which relate to substantially the same subset of native instructions but use the instructions at a substantially differing frequency, allowing the definition of special virtual machine instructions for the most frequently occurring (sequences of) instructions.
- program statements of one task are associated with one virtual machine. This simplifies development of the embedded program, since usually program statements for one task are produced under supervision of one engineer and in this approach the supervisory role can be extended to include the supervision over the production of compacted code and an associated conversion means Depending on the chosen implementation, selection of the conversion means associated with the virtual machine instruction to be executed could incur a delay of the execution. Instead of then selecting a conversion means for individual virtual machine instruction, the overhead may be reduced by switching the conversion means as part of the task switching. As long as then the same tasks executes uninterrupted, no overhead is involved in selecting the appropriate conversion means.
- the same virtual machine may also be used for several tasks which use a similar mix of native instructions in a similar frequency
- the program for a task comprises more than one program module, where at least two of the program modules relate substantially to different subsets of native instructions or use instructions of a similar subset of instructions in substantially different frequencies, then it is preferred to use different virtual machines for those modules.
- a virtual machine may be defined for each or a group of similar objects.
- an instruction module and conversion data for converting the instructions of the module to native instructions is received.
- the processing unit may be supplied with an additional or replacement program module.
- the supply may be local, e.g. , by adding or replacing a ROM with the program module, or loading the program module from a portable storage medium, such as a floppy disk, into a programmable memory.
- the supply may also take place via a network, either a local area network or a wide area network, such as Internet.
- the new software may be a Java applet expressed in Java bytecodes, whereas the original software was written in "C" and optimally compiled to a virtual machine matching the original program together with a corresponding conversion means It will be understood that the defined conversion means can not be used for converting the Java bytecodes since these codes are expressed using a different virtual machine
- an embedded system may initially be supplied with an embedded program expressed using one virtual machine, which preferably is defined for the specific program
- a software update is required, replacing substantially all or a part of the software or adding a software module
- For the entire application program which is then created it may be desired to use a new virtual machine which better reflects the then valid program (which may still contain parts of the old program as well)
- a higher level of code compaction reflected by a different virtual machine
- different virtual machines are used over time, where at each moment in time only one virtual machine is used
- different virtual machines may be used at the same time for different parts of an embedded application program
- Different virtual machines may also be used for programs of a different origin, such an embedded program written in "C" and compacted using a program-specific virtual machine and an program, such as a Java applet, expressed using a different and usually predetermined virtual machine
- the conversion means is of a re -programmable type This allows 'downloading' of a new conversion means into the processing unit whenever a new program is loaded.
- the reprogrammable conversion means may, for instance, be implemented using a re-pogrammable conversion table or microcode, e.g. , stored in (E)EPROM, or using dedicated re-progamma- ble logic, such as an E-PLD.
- the converter comprises dedicated conversion means for each one of the virtual machines.
- the processing unit is created with several dedicated conversion means. In principle it is possible to use one large virtual machine with one corresponding conversion means.
- an embedded program is formed by two program modules of which one module is mainly involved with user interface aspects of the embedded system, requiring mainly native integer instruction, whereas the second module is mainly involved with signal processing, requiring mainlv floating point instructions.
- optimal virtual machines for each of the two modules comprise 256 virtual machine instructions each
- the program modules are expressed using 8-bit codes
- One virtual machine covering both modules can be made bv combining the instruction of the two virtual machines, giving up to 512 virtual machine instructions (at least more than 256). Consequently, the code size will increase since now 9-bit codes are required.
- Such an increase can usually not be compensated by the fact that a combined conversion table may be smaller than two separate conversion table, due to a possible overlap in instructions
- the converter distinguishes between conversion means for different virtual machines based on the location in the instruction memory where the virtual instruction to be executed is stored. For instance, if besides native instructions also virtual machine instructions of two different virtual machines are used, the memory may be subdivided into three regions; one region for each type of instruction. By determining in which region the address of the instruction to be executed lies, the converter can easily detect whether or not conversion is required (native instruction need not be converted) and which conversion means should be used for the conversion.
- a separate indicator e.g. , one or more bits
- a separate indicator may be used for each instruction.
- one global indicator e.g., a register
- one virtual machine instruction is converted into one corresponding native instruction, which is coded more compactly. In this way, the conversion can be very simple.
- one virtual machine instruction is converted into a predetermined sequence of a plurality of native instructions, giving a further level of compaction.
- a sequencer is used to control the feeding of the sequence of native instructions to the microcontroller core, for instance by inhibiting an increment of the instruction pointer (program counter) of the microcontroller while the sequence is being fed and enabling an increment when a sequence has been completed.
- the processing unit comprises an instruction fetcher for fetching an instruction from the instruction memory under control of its own instruction counter. Whenever a sequence has been completed, changing of the counter is enabled, and the instruction counter is set to a different value in response to a change of an instruction pointer (program counter) of the microcontroller core. While a sequence is being processed, a change of value of the instruction counter is inhibited.
- Figure 1 illustrates four possible architectural options of locating the converter in the processing unit
- Figure 2 illustrates the process of defining the virtual machine and associated converter
- Figure 3 illustrates the process for a program foremd of several coherent groups of program statements
- Figure 4 shows a block diagram of the converter
- Figure 1 illustrates four possible architectural options of locating the converter in the processing unit 100.
- Three main components of the processing unit 100 are the microcontroller 110, the instruction memory 120 and a pre-processor 130.
- the preprocessor 130 comprises the converter 132.
- the microcontroller 110 comprises the instruction memory 120 and the pre-processor 130. As such, the processing unit 100 is not shown explicitly.
- the instruction memory 120 and/or the pre-processor 130 may be located outside the microcontroller 110, where the microcontroller bus 140 is extended outside the microcontroller 110 and, for instance, coupled to an external bus such as PCI
- the instruction memory 120 contains virtual machine instructions, such as instructions for a stack machine
- the instruction memory may also be used for storing data The invnetion is not limited to Harvard architecture, wherein data and instructions are separate
- the microcontroller 110 comprises a processor 112 with a predetermined microcontroller core 114, referred to as a native machine, for executing native instructions from a predetermined set of microcontroller specific instructions
- An example of a microcontroller suitable for executing embedded software is a RISC-type microcontroller, like the MIPS PR3001 range of microprocessors
- the processor may comprise an instruction cache 1 16 for storing native instructions before executing the instructions
- Fig 1A the main components of the processing unit are interconnected via a general peripheral interconnect bus 140, such as the PI bus
- the pre-processor 130 is a peripheral on the bus
- the pre-processor 130 may act as a memory-mapped peripheral, where a predetermined range of addresses is allocated to the pre-processor
- the pre-processor 130 issues the native instruction on the bus 140
- the pre-processor 130 fetches a virmal machine instruction from the instruction memory 120 via the bus 140
- the pre-processor 130 is located in between the procesor 112 and the instruction memory 120 If the pre-processor 130 needs to distinguish between native and virmal machine instructions, these configurations may delay execution of native instructions stored in the instruction memory 120 For reasons of clarity not all elements shown in Fig 1A are repeated in Fig IB 1C and ID
- the pre-processor 130 is embedded in the processor 1 12
- the pre-processor 130 is preferably located between an instruction cache 116 of the processor 1 12 and the core 1 14 This configuration allows for optimal performance but unlike the configurations of Figs 1A, IB and 1C, requires changes to the microcontroller 110 and, as such, the pre-processor 130 can not as an off-the-shelf design be used for different types of processors w ith the same type of core 114
- a program-specific virtual machine with a corresponding set of virtual machine instructions is defined for the program statements of a source program which needs to be executed by the processing unit 100
- an associated converter 132 is defined for converting virtual machine structions into native instructions of the microcontroller core
- the converter 132 provides for each of the virtual machine instructions one or, usually, a sequence of corresponding native instructions required for executing the virtual machine instruction of the native core 114
- Figure 2 illustrates the process of defining the virtual machine and associated converter
- the source program 200 is analysed Based on the analysis (e g , frequency of occurrence of operations), m step 210 a program-specific virtual machine 215 is defined
- an associated converter 225 is defined and in step 230 the source program is expressed m instructions of the virmal machine resulting in code 235
- the virtual machine is defined such that the code requires less storage space in the instruction memory compared to using only native instructions for expressing the program statements
- the program-specific virmal machine is defined by translating the program to virtual machine instructions of a predetermined virtual machine
- a virtual machine such as a stack machine
- a virtual machine is chosen which is known to give a compact representation Due to the fact that a stack machine does not use explicit registers for storing operands, but instead operands are stored on the stack and operators always act on top element(s) of the stack, the number of operands which can be used is less restricted and management of the operands is simpler for a stack machine This makes it easier to build a compiler for a stack based machine than for a register based machine Furthermore, stack machine instructions tend to have a simpler structure than most register based machines However, it will be appreciated that also a suitable register based machine may be used To illustrate the invention, the stack machine of Annex A is used A sample program (which solves the eight queens problem) written in the "C" programming language is shown in Annex B The translation of the program to stack code of the ⁇ irtual machine of Annex A is shown
- a program specific virtual machine is defined in the following way.
- the source program is converted to an intermediate level representation of so-called expression trees based on a predetermined virtual machine.
- An expression tree is constructed of nodes representing basic operations of the virtual machine.
- the expression tree represents the computation resulting from performing the basic operations of the nodes of the tree in a given sequence (e.g. , postfix order).
- the conversion of the program to expression trees may be performed using the parsing phase of a compiler, such as the Tight "C" compiler lcc' of Fraser and Hanson.
- the expression trees and coherent tree fragments are identified. Each of the trees and fragments is a candidate to be represented by a superinstruction.
- the tree or tree fragment which gives most savings in code size is represented by a superinstruction.
- the superinstruction is added to the virmal machine.
- the program is expressed in the new set of virtual machine instructions to determine the saving. New superinstructions are added as long as still room is available for adding new instructions (e.g. , if the virtual machine instructions need to be stored as bytes, the number of instructions is limited to 256) or until no saving are achieved any more.
- the source program is expressed in instructions of the program-specific virtual machine and conversion data is generated.
- the resulting code is stored in the instruction memory 120.
- the code is usually stored in a ROM, which is mask-programmed, or a programmable ROM, such as a PROM or (E)EPROM.
- the generated conversion data is represented in the converter 132 of the processing unit 100.
- the converter 132 may, for instance, be implemented using a conversion table or microcode stored in ROM.
- the converter 132 may also be implemented using logic, such as a PLD.
- a re-programmable converter the same approach can be used based on the respective re-programmable techniques, such as (E)EP- ROM or E-PLD.
- FIG. 3 illustrates a further embodiment according to the invention, wherein the source program 300, e.g. , programmed in "C" , is split in step 310 into several coherent groups of program statements, such as program modules, objects or task-specific code. Shown are modules 312 and 316. It will be appreciated that no explicit splitting may be required and the source program may already be available in a suitable modular organisation.
- a program group specific virtual machine is defined (step 330) with a corresponding set of virtual machine instructions in a way similar to steps 205 and 210 of Fig. 2. Shown are the respective virtual machines 332 and 336. In step 340.
- step 360 for the program group specific virtual machines 332 and 336 respective conversion means 362 and 366 are generated for converting virtual machine instructions into native instructions of the microcontroller core
- step 370 the conversion means 362 and 366 are represented in the processing unit 100, for instance by programming a conversion table or logic in the processing unit 100
- the converter 132 comprises a specific conversion means for each of the program groups
- step 390 selection data is stored in the processing unit During execution a virtual machine instruction is fetched from the instruction memory 120 The selection data is then used to locate the conversion means associated w ith the virtual machine to which the virtual machine instruction belongs
- FIG. 4 shows a block diagram of the converter 132 wherein the converter 132 comprises several conversion means (shown are 400, 410 and 420) Each of the conversion means is used for converting virmal machine instructions of a specific v irtual machine It will be appreciated that the converter 132 mav comprise fully autonomous conversion means, each capable of performing the full conversion Alternatively, the converter 132 may use some shared logic under control of separate conversion data (such as a table) for each of the virtual machines
- the processing unit 100 comprises the selection data 430
- the selection data may be represented in any suitable way, e g , stored in the instruction memory 120 or, if the conversion means is stored (partly) as data stored in combination with the conversion means
- the selection data 430 may also take the form of a register m the converter 132 loaded from a memory Various forms of selection data may be used In a further embodiment, the address range of the instruction memory
- an address sub-range is reserved for storing virtual machine instructions of only one virtual machine
- an address sub-range is also reserved for storing native instructions
- Such native instructions may, for instance, be used to initialise the system or to allow certain software modules, such as drivers or special parts of the embedded software application, to be compiled to native instructions for optimal performance
- the selection data indicates for each of the defined address sub-ranges which one of the conversion means 400, 410 or 420 should be used for converting an instruction fetched by the instruction fetcher 134 to native instructions
- the converter 132 comprises a detector 440 for selectively directing an instruction fetched from a location in the instruction memory 120 to one of the conversion means 400, 410 or 420, based on the selection data.
- the detector 440 ensures that these instructions are directly supplied to the feeder 136 for supply to the microcontroller core 114.
- the information may also be stored in direct association with the instruction. For instance one or more bits of each entry in the instruction memory 120 may be reserved to differentiate between virmal machines and/or between native code or virtual code. For instance, if only two virtual machines are used, where the instructions require 7 bit, an eighth bit can be used to indicate the virmal machine to which the instruction belongs and the associated conversion means. Obviously, this technique may be combined with differentiating based on addresses.
- the selection data may be stored in a register where the register is set to indicate a different conversion means each time a switch occurs between virtual machines.
- a special instruction e.g. , a form of a jump instruction
- Such implementation-supporting instructions can be mixed with the virtual machine/native instructions in the instruction memory.
- the processing unit 100 comprises a sequencer 450 coupled in between the converter 132 and the microcontroller core 1 14 for sequentially feeding the sequence of native instructions to the microcontroller core 114.
- the sequencer 450 may be implemented using conventional components, such as a counter, which may, for instance, be incremented as a result of a trigger from the microcontroller core indicating that a new instruction is required (e.g. , an increment of the instruction counter of the core).
- a change of the instruction pointer (also referred to as program counter) of the microcontroller core results in the fetcher 134 fetching an instruction from the instruction memory 120 and the feeder 136 supplying the instruction to the microcontroller core 114.
- the processing unit 100 further comprises inhibiting means 460 for inhibiting fetching an instruction from the instruction memory during the feeding of the sequence.
- the sequencing and inhibiting may be performed in several ways.
- the inhibiting means 460 is operative to perform the inhibiting by obstructing an increment of the instruction pointer of the microcon- troller core 114. This may require a small modification to the core 114. For instance, an additional control line into the core 114 may allow selective inhibiting of the instruction counter, where the inhibiting means 460 inhibits the increment whenever instructions from the sequence are being supplied and enables an increment when a sequence has been fully supplied.
- the instruction fetcher 134 maintains its own instruction counter 135, separate from the instruction pointer of the microcontroller core 112.
- the inhibiting means 460 controls when an increment (or more general a change) of the instruction pointer of the microcontroller results in a change of the instruction counter 135 of the instruction fetcher 134. Similar as described above, the inhibiting means 460 inhibits a change of the instruction counter 135 whenever instructions from the sequence are being supplied and enables a change when a sequence has been fully supplied. As a result of a change of the instruction counter 135, the instruction fetcher 134 will normally fetch a new instruction from the instruction memory 1 12, from an address indicated by the instruction counter.
- the instruction fetcher 134 may fetch several instructions from the memory in one read operation (e.g. , four one-byte instructions may be read as one 32-bit word). In this way, not every change of the instruction counter 135 needs to result in actually fetching a new instruction.
- a program module expressed in virtual machine instructions of a further virtual machine is received, e.g.. via a network or from a local background memory.
- An example of such a program module is a Java applet.
- the received program module is stored in the instruction memory 120.
- conversion data is received.
- the conversion data may for instance specify a conversion table for a table based conversion means or E-PLD programming data for a PLD based conversion means.
- the conversion data is stored in the processing unit for subsequent use by a further conversion means of the converter 132.
- selection data is stored in the processing unit associating each further virmal machine instruction with the conversion data.
- the further conversion means is operated under control of the conversion data indicated by the selection data.
- the converter 132 may comprise a table for converting a virmal machine instruction to a sequence of native instructions.
- a one dimensio- nal table may be used, where each cell of the table comprises a sequence of native instructions for one corresponding virmal machine instruction.
- the cell number may correspond to the value of the corresponding virmal machine instruction.
- Such a translation table 500 is shown in Fig.
- a code index table 510 may be used, which for each virtual machine instruction (VMI 1 to VMI N) indicates the starting point of the corresponding sequence in the translation table 500.
- VMI 1 to VMI N For the cell of the translation table 500 which corresponds to VMI 3 the related sequence 520 of native instruction NI 1 to NI M are shown.
- Java byte code bipush /i used for sign extending byte n and placing the result on top of the stack.
- This virtual machine instruction consists of two bytes ⁇ 0x16 and 72 ⁇ , where the first byte specifies the operation and the second byte provides the parameter 72.
- the instruction may be converted to the following sequence of native MIPS instructions: ori $a0, $0, n/* Load register SaO with constant n */ sll SaO, SaO, 24/* Shift left by 24 bits */ sra $a0. SaO, 24/* Arithmetic shift right, causing sign extension, by
- a virtual machine instruction may be parameter ised, where an operation code is followed by at least one operand.
- the converter 132 comprises a conversion table 500, where native instructions are represented either by the full code or by an instruction skeleton.
- the instruction addi Stosp, -4 (last instruction of the sequence of the previous example) contains no variable parts and may be located in full as a 4-byte entry in the table.
- the instruction ori $a0, $0, n (first instruction of the sequence of the previous example) contains a variable part and may be located in the table as a skeleton, not specifying the variable part (being n).
- the entry in the table for an instruction skeleton is the same width as a full instruction (e.g. , 4-bytes for a MIPS processor), allowing a uniform table.
- Further information may be located in the table (or in separate table(s)) for indicating how the unspecified part of the native instruction skeleton should be filled in
- microprogramming is used to fill in the unspecified parts
- the further information may then comprise or indicate micro code
- the virtual machine is a stack oriented machine
- the stack or at least the top elements of the stack are mapped onto registers of the microcontroller 1 10
- the memory stack (with the virtual machine stack) is mapped to the register stack
- registers $rl , Sr2 and $r3 contain three successive elements ot the memory stack, where initially Sri corresponds to the first empty location of the memory stack (above the top of the stack), Sr2 contains the top of the memorv stack, and $r3 contains the second element of the memory stack
- the Ja a byte code bipush n ma ⁇ be converted to the following sequence of native MIPS instructions on Sri , SO, n sll $rl , Sri, 24 sra Sri, Sri, 24 After this operation, $rl contains the top of the memorv stack
- the Jav a byte code (a virtual machine instruction) for integer addition (0x60) may be converted to the following sequence of MIPS instructions, starting from the same position where initially Sri corresponds to the first empty location of the memorv stack (above the top of the stack), Sr2 contains the top of the memorv stack, and $r3 contains the second element of the memory stack add Sr3, $r2, $r3 After this operation, $r3 contains the top of the memory stack
- the position of the top of the memory stack (I e , which register contains the top of the memory stack) is indicated using a register 138 of the converter 132
- the converter uses the register 138, referred to as the Register Stack Pointer (RSP), to generate the appropriate native instructions
- RSP Register Stack Pointer
- micropro- grammmg is used to specify the register operands of the native instructions
- such operands are also stored in the translation table 500 using instruction skeletons
- the Java byte code b ⁇ ush n may be converted to the following sequence of native MIPS instructions under control of the corresponding micro code:
- CVU CSIP convert from unsigned
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98941638A EP0941508B1 (en) | 1997-10-02 | 1998-09-21 | Variable instruction set computer |
JP52133799A JP4018158B2 (en) | 1997-10-02 | 1998-09-21 | Variable instruction set computer |
DE69836902T DE69836902T2 (en) | 1997-10-02 | 1998-09-21 | COMPUTER SETTING ON VARIABLE INSTRUCTIONS |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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EP97203033 | 1997-10-02 | ||
EP97203033.2 | 1997-10-02 | ||
EP97203905.1 | 1997-12-12 | ||
EP97203905 | 1997-12-12 |
Publications (2)
Publication Number | Publication Date |
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WO1999018485A2 true WO1999018485A2 (en) | 1999-04-15 |
WO1999018485A3 WO1999018485A3 (en) | 1999-07-01 |
Family
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Application Number | Title | Priority Date | Filing Date |
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PCT/IB1998/001453 WO1999018485A2 (en) | 1997-10-02 | 1998-09-21 | Variable instruction set computer |
Country Status (5)
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US (1) | US6292883B1 (en) |
EP (1) | EP0941508B1 (en) |
JP (1) | JP4018158B2 (en) |
DE (1) | DE69836902T2 (en) |
WO (1) | WO1999018485A2 (en) |
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Also Published As
Publication number | Publication date |
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DE69836902T2 (en) | 2007-10-18 |
JP2001508908A (en) | 2001-07-03 |
JP4018158B2 (en) | 2007-12-05 |
DE69836902D1 (en) | 2007-03-08 |
EP0941508A1 (en) | 1999-09-15 |
US6292883B1 (en) | 2001-09-18 |
EP0941508B1 (en) | 2007-01-17 |
WO1999018485A3 (en) | 1999-07-01 |
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