WO2002041104A3 - An instruction set architecture to aid code generation for hardware platforms multiple heterogeneous functional units - Google Patents

An instruction set architecture to aid code generation for hardware platforms multiple heterogeneous functional units Download PDF

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Publication number
WO2002041104A3
WO2002041104A3 PCT/US2001/043255 US0143255W WO0241104A3 WO 2002041104 A3 WO2002041104 A3 WO 2002041104A3 US 0143255 W US0143255 W US 0143255W WO 0241104 A3 WO0241104 A3 WO 0241104A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction set
functional units
code generation
set architecture
hardware platforms
Prior art date
Application number
PCT/US2001/043255
Other languages
French (fr)
Other versions
WO2002041104A9 (en
WO2002041104A2 (en
Inventor
Krishna Palem
Hitesh Patel
Sudhakar Yalamanchili
Original Assignee
Proceler Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proceler Inc filed Critical Proceler Inc
Priority to AU2002226901A priority Critical patent/AU2002226901A1/en
Publication of WO2002041104A2 publication Critical patent/WO2002041104A2/en
Publication of WO2002041104A3 publication Critical patent/WO2002041104A3/en
Publication of WO2002041104A9 publication Critical patent/WO2002041104A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Abstract

The present invention affords a system and method for simplifying the development and deployment of high-performance embedded applications on reconfigurable computing systems (100). The invention provides a single, high-level development process, enabling system developers to utilize various programming languages to program both the reconfigurable devices (103-105) and the microprocessor (102) of a reconfigurable computing system.
PCT/US2001/043255 2000-11-17 2001-11-19 An instruction set architecture to aid code generation for hardware platforms multiple heterogeneous functional units WO2002041104A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002226901A AU2002226901A1 (en) 2000-11-17 2001-11-19 An instruction set architecture to aid code generation for hardware platforms multiple heterogeneous functional units

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71557800A 2000-11-17 2000-11-17
US09/715,578 2000-11-17

Publications (3)

Publication Number Publication Date
WO2002041104A2 WO2002041104A2 (en) 2002-05-23
WO2002041104A3 true WO2002041104A3 (en) 2002-08-08
WO2002041104A9 WO2002041104A9 (en) 2003-02-13

Family

ID=24874637

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043255 WO2002041104A2 (en) 2000-11-17 2001-11-19 An instruction set architecture to aid code generation for hardware platforms multiple heterogeneous functional units

Country Status (2)

Country Link
AU (1) AU2002226901A1 (en)
WO (1) WO2002041104A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675804A (en) * 1995-08-31 1997-10-07 International Business Machines Corporation System and method for enabling a compiled computer program to invoke an interpretive computer program
US5764989A (en) * 1996-02-29 1998-06-09 Supercede, Inc. Interactive software development system
US6295561B1 (en) * 1998-06-30 2001-09-25 At&T Corp System for translating native data structures and specific message structures by using template represented data structures on communication media and host machines

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675804A (en) * 1995-08-31 1997-10-07 International Business Machines Corporation System and method for enabling a compiled computer program to invoke an interpretive computer program
US5764989A (en) * 1996-02-29 1998-06-09 Supercede, Inc. Interactive software development system
US6295561B1 (en) * 1998-06-30 2001-09-25 At&T Corp System for translating native data structures and specific message structures by using template represented data structures on communication media and host machines

Also Published As

Publication number Publication date
WO2002041104A9 (en) 2003-02-13
WO2002041104A2 (en) 2002-05-23
AU2002226901A1 (en) 2002-05-27

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