WO2007067562A3 - Methods and apparatus for multi-core processing with dedicated thread management - Google Patents

Methods and apparatus for multi-core processing with dedicated thread management Download PDF

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Publication number
WO2007067562A3
WO2007067562A3 PCT/US2006/046438 US2006046438W WO2007067562A3 WO 2007067562 A3 WO2007067562 A3 WO 2007067562A3 US 2006046438 W US2006046438 W US 2006046438W WO 2007067562 A3 WO2007067562 A3 WO 2007067562A3
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WO
WIPO (PCT)
Prior art keywords
methods
thread
thread management
management
core processing
Prior art date
Application number
PCT/US2006/046438
Other languages
French (fr)
Other versions
WO2007067562A2 (en
Inventor
Aaron S Kurland
Original Assignee
Boston Circuits Inc
Aaron S Kurland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boston Circuits Inc, Aaron S Kurland filed Critical Boston Circuits Inc
Priority to EP06839037A priority Critical patent/EP1963963A2/en
Priority to JP2008544448A priority patent/JP2009519513A/en
Publication of WO2007067562A2 publication Critical patent/WO2007067562A2/en
Publication of WO2007067562A3 publication Critical patent/WO2007067562A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for dedicated thread management in a CMP having processing units, interface blocks, and function blocks interconnected by an on-chip network. In various embodiments, thread management occurs independent of any particular processing unit allowing for fast, low-latency switching of threads without incurring the overhead associated with a software-based thread-management thread.
PCT/US2006/046438 2005-12-06 2006-12-06 Methods and apparatus for multi-core processing with dedicated thread management WO2007067562A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06839037A EP1963963A2 (en) 2005-12-06 2006-12-06 Methods and apparatus for multi-core processing with dedicated thread management
JP2008544448A JP2009519513A (en) 2005-12-06 2006-12-06 Multi-core arithmetic processing method and apparatus using dedicated thread management

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74267405P 2005-12-06 2005-12-06
US60/742,674 2005-12-06

Publications (2)

Publication Number Publication Date
WO2007067562A2 WO2007067562A2 (en) 2007-06-14
WO2007067562A3 true WO2007067562A3 (en) 2007-10-25

Family

ID=37714655

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/046438 WO2007067562A2 (en) 2005-12-06 2006-12-06 Methods and apparatus for multi-core processing with dedicated thread management

Country Status (5)

Country Link
US (1) US20070150895A1 (en)
EP (1) EP1963963A2 (en)
JP (1) JP2009519513A (en)
CN (1) CN101366004A (en)
WO (1) WO2007067562A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236576B (en) * 2008-01-31 2011-12-07 复旦大学 Interconnecting model suitable for heterogeneous reconfigurable processor

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299334A (en) * 2006-05-02 2007-11-15 Sony Computer Entertainment Inc Method for controlling information processing system and computer
US8055951B2 (en) * 2007-04-10 2011-11-08 International Business Machines Corporation System, method and computer program product for evaluating a virtual machine
US20080307422A1 (en) * 2007-06-08 2008-12-11 Kurland Aaron S Shared memory for multi-core processors
US8059670B2 (en) * 2007-08-01 2011-11-15 Texas Instruments Incorporated Hardware queue management with distributed linking information
US7886172B2 (en) * 2007-08-27 2011-02-08 International Business Machines Corporation Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management
US8245232B2 (en) * 2007-11-27 2012-08-14 Microsoft Corporation Software-configurable and stall-time fair memory access scheduling mechanism for shared memory systems
CN101227486B (en) * 2008-02-03 2010-11-17 浙江大学 Transport protocols suitable for multiprocessor network on chip
US8223779B2 (en) * 2008-02-07 2012-07-17 Ciena Corporation Systems and methods for parallel multi-core control plane processing
GB0808576D0 (en) * 2008-05-12 2008-06-18 Xmos Ltd Compiling and linking
US8561073B2 (en) * 2008-09-19 2013-10-15 Microsoft Corporation Managing thread affinity on multi-core processors
US8140832B2 (en) * 2009-01-23 2012-03-20 International Business Machines Corporation Single step mode in a software pipeline within a highly threaded network on a chip microprocessor
US8271809B2 (en) * 2009-04-15 2012-09-18 International Business Machines Corporation On-chip power proxy based architecture
US8650413B2 (en) * 2009-04-15 2014-02-11 International Business Machines Corporation On-chip power proxy based architecture
US9164969B1 (en) * 2009-09-29 2015-10-20 Cadence Design Systems, Inc. Method and system for implementing a stream reader for EDA tools
KR101191530B1 (en) 2010-06-03 2012-10-15 한양대학교 산학협력단 Multi-core processor system having plurality of heterogeneous core and Method for controlling the same
US8527970B1 (en) * 2010-09-09 2013-09-03 The Boeing Company Methods and systems for mapping threads to processor cores
US9552206B2 (en) * 2010-11-18 2017-01-24 Texas Instruments Incorporated Integrated circuit with control node circuitry and processing circuitry
US8954546B2 (en) 2013-01-25 2015-02-10 Concurix Corporation Tracing with a workload distributor
US8924941B2 (en) 2013-02-12 2014-12-30 Concurix Corporation Optimization analysis using similar frequencies
US8997063B2 (en) 2013-02-12 2015-03-31 Concurix Corporation Periodicity optimization in an automated tracing system
US20130283281A1 (en) 2013-02-12 2013-10-24 Concurix Corporation Deploying Trace Objectives using Cost Analyses
US9665474B2 (en) 2013-03-15 2017-05-30 Microsoft Technology Licensing, Llc Relationships derived from trace data
US10423216B2 (en) * 2013-03-26 2019-09-24 Via Technologies, Inc. Asymmetric multi-core processor with native switching mechanism
US9575874B2 (en) 2013-04-20 2017-02-21 Microsoft Technology Licensing, Llc Error list and bug report analysis for configuring an application tracer
US9292415B2 (en) 2013-09-04 2016-03-22 Microsoft Technology Licensing, Llc Module specific tracing in a shared module environment
US9772927B2 (en) 2013-11-13 2017-09-26 Microsoft Technology Licensing, Llc User interface for selecting tracing origins for aggregating classes of trace data
CN103838631B (en) * 2014-03-11 2017-04-19 武汉科技大学 Multi-thread scheduling realization method oriented to network on chip
US9330433B2 (en) 2014-06-30 2016-05-03 Intel Corporation Data distribution fabric in scalable GPUs
US10983931B2 (en) * 2015-04-30 2021-04-20 Microchip Technology Incorporated Central processing unit with enhanced instruction set
US9841999B2 (en) * 2015-07-31 2017-12-12 Futurewei Technologies, Inc. Apparatus and method for allocating resources to threads to perform a service
US10860374B2 (en) * 2015-09-26 2020-12-08 Intel Corporation Real-time local and global datacenter network optimizations based on platform telemetry data
US10509677B2 (en) 2015-09-30 2019-12-17 Lenova (Singapore) Pte. Ltd. Granular quality of service for computing resources
US9519583B1 (en) * 2015-12-09 2016-12-13 International Business Machines Corporation Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute
CN108462658B (en) * 2016-12-12 2022-01-11 阿里巴巴集团控股有限公司 Object allocation method and device
US10614406B2 (en) 2018-06-18 2020-04-07 Bank Of America Corporation Core process framework for integrating disparate applications
CN109522112B (en) * 2018-12-27 2022-06-17 上海识致信息科技有限责任公司 Data acquisition system
CN113227917A (en) * 2019-12-05 2021-08-06 Mzta科技中心有限公司 Modular PLC automatic configuration system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US20020147760A1 (en) * 1996-07-12 2002-10-10 Nec Corporation Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
US20030074542A1 (en) * 2001-09-03 2003-04-17 Matsushita Electric Industrial Co., Ltd. Multiprocessor system and program optimizing method
WO2006074024A2 (en) * 2004-12-30 2006-07-13 Intel Corporation A mechanism for instruction set based thread execution on a plurality of instruction sequencers

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956748A (en) * 1997-01-30 1999-09-21 Xilinx, Inc. Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization
US6044453A (en) * 1997-09-18 2000-03-28 Lg Semicon Co., Ltd. User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure
US6275831B1 (en) * 1997-12-16 2001-08-14 Starfish Software, Inc. Data processing environment with methods providing contemporaneous synchronization of two or more clients
US6115646A (en) * 1997-12-18 2000-09-05 Nortel Networks Limited Dynamic and generic process automation system
US6134675A (en) * 1998-01-14 2000-10-17 Motorola Inc. Method of testing multi-core processors and multi-core processor testing device
US6269425B1 (en) * 1998-08-20 2001-07-31 International Business Machines Corporation Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system
US6449622B1 (en) * 1999-03-08 2002-09-10 Starfish Software, Inc. System and methods for synchronizing datasets when dataset changes may be received out of order
GB9825102D0 (en) * 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
US6247135B1 (en) * 1999-03-03 2001-06-12 Starfish Software, Inc. Synchronization process negotiation for computing devices
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6578065B1 (en) * 1999-09-23 2003-06-10 Hewlett-Packard Development Company L.P. Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory
US6629271B1 (en) * 1999-12-28 2003-09-30 Intel Corporation Technique for synchronizing faults in a processor having a replay system
US6550020B1 (en) * 2000-01-10 2003-04-15 International Business Machines Corporation Method and system for dynamically configuring a central processing unit with multiple processing cores
US6694336B1 (en) * 2000-01-25 2004-02-17 Fusionone, Inc. Data transfer and synchronization system
US6922417B2 (en) * 2000-01-28 2005-07-26 Compuware Corporation Method and system to calculate network latency, and to display the same field of the invention
US6931641B1 (en) * 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors
US20050055382A1 (en) * 2000-06-28 2005-03-10 Lounas Ferrat Universal synchronization
US6691216B2 (en) * 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
US6895479B2 (en) * 2000-11-15 2005-05-17 Texas Instruments Incorporated Multicore DSP device having shared program memory with conditional write protection
US8762581B2 (en) * 2000-12-22 2014-06-24 Avaya Inc. Multi-thread packet processor
US6665755B2 (en) * 2000-12-22 2003-12-16 Nortel Networks Limited External memory engine selectable pipeline architecture
US8463744B2 (en) * 2001-01-03 2013-06-11 International Business Machines Corporation Method and system for synchronizing data
US6976155B2 (en) * 2001-06-12 2005-12-13 Intel Corporation Method and apparatus for communicating between processing entities in a multi-processor
US7320011B2 (en) * 2001-06-15 2008-01-15 Nokia Corporation Selecting data for synchronization and for software configuration
US20030005380A1 (en) * 2001-06-29 2003-01-02 Nguyen Hang T. Method and apparatus for testing multi-core processors
JP3661614B2 (en) * 2001-07-12 2005-06-15 日本電気株式会社 Cache memory control method and multiprocessor system
US7134002B2 (en) * 2001-08-29 2006-11-07 Intel Corporation Apparatus and method for switching threads in multi-threading processors
US6779065B2 (en) * 2001-08-31 2004-08-17 Intel Corporation Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads
US6681274B2 (en) * 2001-10-15 2004-01-20 Advanced Micro Devices, Inc. Virtual channel buffer bypass for an I/O node of a computer system
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
US6804632B2 (en) * 2001-12-06 2004-10-12 Intel Corporation Distribution of processing activity across processing hardware based on power consumption considerations
US7500240B2 (en) * 2002-01-15 2009-03-03 Intel Corporation Apparatus and method for scheduling threads in multi-threading processors
US7069442B2 (en) * 2002-03-29 2006-06-27 Intel Corporation System and method for execution of a secured environment initialization instruction
US20030229740A1 (en) * 2002-06-10 2003-12-11 Maly John Warren Accessing resources in a microprocessor having resources of varying scope
US20040019722A1 (en) * 2002-07-25 2004-01-29 Sedmak Michael C. Method and apparatus for multi-core on-chip semaphore
US6976131B2 (en) * 2002-08-23 2005-12-13 Intel Corporation Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US20040049628A1 (en) * 2002-09-10 2004-03-11 Fong-Long Lin Multi-tasking non-volatile memory subsystem
US7076609B2 (en) * 2002-09-20 2006-07-11 Intel Corporation Cache sharing for a chip multiprocessor or multiprocessing system
US7089340B2 (en) * 2002-12-31 2006-08-08 Intel Corporation Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives
US7020748B2 (en) * 2003-01-21 2006-03-28 Sun Microsystems, Inc. Cache replacement policy to mitigate pollution in multicore processors
US7146514B2 (en) * 2003-07-23 2006-12-05 Intel Corporation Determining target operating frequencies for a multiprocessor system
US7873785B2 (en) * 2003-08-19 2011-01-18 Oracle America, Inc. Multi-core multi-thread processor
US20050108704A1 (en) * 2003-11-14 2005-05-19 International Business Machines Corporation Software distribution application supporting verification of external installation programs
US20050125582A1 (en) * 2003-12-08 2005-06-09 Tu Steven J. Methods and apparatus to dispatch interrupts in multi-processor systems
US7391776B2 (en) * 2003-12-16 2008-06-24 Intel Corporation Microengine to network processing engine interworking for network processors
US20050154573A1 (en) * 2004-01-08 2005-07-14 Maly John W. Systems and methods for initializing a lockstep mode test case simulation of a multi-core processor design
US8533716B2 (en) * 2004-03-31 2013-09-10 Synopsys, Inc. Resource management in a multicore architecture
US20060095905A1 (en) * 2004-11-01 2006-05-04 International Business Machines Corporation Method and apparatus for servicing threads within a multi-processor system
US9063785B2 (en) * 2004-11-03 2015-06-23 Intel Corporation Temperature-based thread scheduling
US20060107262A1 (en) * 2004-11-03 2006-05-18 Intel Corporation Power consumption-based thread scheduling
US7765547B2 (en) * 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
JP4606142B2 (en) * 2004-12-01 2011-01-05 株式会社ソニー・コンピュータエンタテインメント Scheduling method, scheduling apparatus, and multiprocessor system
US8230423B2 (en) * 2005-04-07 2012-07-24 International Business Machines Corporation Multithreaded processor architecture with operational latency hiding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020147760A1 (en) * 1996-07-12 2002-10-10 Nec Corporation Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US20030074542A1 (en) * 2001-09-03 2003-04-17 Matsushita Electric Industrial Co., Ltd. Multiprocessor system and program optimizing method
WO2006074024A2 (en) * 2004-12-30 2006-07-13 Intel Corporation A mechanism for instruction set based thread execution on a plurality of instruction sequencers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236576B (en) * 2008-01-31 2011-12-07 复旦大学 Interconnecting model suitable for heterogeneous reconfigurable processor

Also Published As

Publication number Publication date
WO2007067562A2 (en) 2007-06-14
US20070150895A1 (en) 2007-06-28
JP2009519513A (en) 2009-05-14
EP1963963A2 (en) 2008-09-03
CN101366004A (en) 2009-02-11

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