WO2007080437A3 - Process simulation software and hardware architecture and method - Google Patents

Process simulation software and hardware architecture and method Download PDF

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Publication number
WO2007080437A3
WO2007080437A3 PCT/HU2007/000002 HU2007000002W WO2007080437A3 WO 2007080437 A3 WO2007080437 A3 WO 2007080437A3 HU 2007000002 W HU2007000002 W HU 2007000002W WO 2007080437 A3 WO2007080437 A3 WO 2007080437A3
Authority
WO
WIPO (PCT)
Prior art keywords
software
software modules
establish
connection means
rules
Prior art date
Application number
PCT/HU2007/000002
Other languages
French (fr)
Other versions
WO2007080437A9 (en
WO2007080437A2 (en
Inventor
Bela Csukas
Gyoengyi Bankuti
Sandor Balogh
Original Assignee
Kaposvari Egyetern
Folyamatinformatika Kutato Fej
Bela Csukas
Gyoengyi Bankuti
Sandor Balogh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaposvari Egyetern, Folyamatinformatika Kutato Fej, Bela Csukas, Gyoengyi Bankuti, Sandor Balogh filed Critical Kaposvari Egyetern
Publication of WO2007080437A2 publication Critical patent/WO2007080437A2/en
Publication of WO2007080437A9 publication Critical patent/WO2007080437A9/en
Publication of WO2007080437A3 publication Critical patent/WO2007080437A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

Abstract

There is disclosed a software architecture with multiple substantially equal first software modules and multiple substantially equal second software modules. The first software modules are programmed to represent a passive element and to establish on the basis of a set of predetermined rules a value of a state parameter. The set of predetermined rules establishing the values of the state parameters are defined so that a resulting output value of the rules may be calculated substantially without repeated cycles. The second software modules are programmed to represent an active element and to establish on the basis of a set of predetermined rules a change of a value of a state parameter. The set of predetermined rules are defined so that a resulting output value of the rules may be calculated substantially without repeated cycles. The suggested software architecture further comprises first connection means for communicating an output value of a state parameter from a first software module to the input of one or more second software modules, and second connection means for communicating an output value of a change of a state parameter from a second software module to the input of one or more first software modules. The suggested software architecture further comprises cycle control means cyclically causing the first software modules to establish the output values of state parameters substantially simultaneously, the first connection means to communicate output values from the first software module to the second software modules, the second software modules to establish the output values from their respective input state parameters substantially simultaneously, and the second connection means to communicate the output values from the second software module to the first software modules. There is further disclosed a hardware architecture for executing the software, and a method underlying the software.
PCT/HU2007/000002 2006-01-16 2007-01-15 Process simulation software and hardware architecture and method WO2007080437A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HUP0600034 2006-01-16
HU0600034A HU0600034D0 (en) 2006-01-16 2006-01-16 Process simulation software and hardware architecture and method

Publications (3)

Publication Number Publication Date
WO2007080437A2 WO2007080437A2 (en) 2007-07-19
WO2007080437A9 WO2007080437A9 (en) 2008-01-10
WO2007080437A3 true WO2007080437A3 (en) 2008-02-14

Family

ID=89986521

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/HU2007/000002 WO2007080437A2 (en) 2006-01-16 2007-01-15 Process simulation software and hardware architecture and method

Country Status (2)

Country Link
HU (1) HU0600034D0 (en)
WO (1) WO2007080437A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692193A (en) * 1994-03-31 1997-11-25 Nec Research Institute, Inc. Software architecture for control of highly parallel computer systems
WO2001098871A2 (en) * 2000-06-19 2001-12-27 P.C. Krause And Associates, Inc. Distributed simulation
US20020133325A1 (en) * 2001-02-09 2002-09-19 Hoare Raymond R. Discrete event simulator
US20020169785A1 (en) * 2000-12-29 2002-11-14 Netemeyer Stephen C. Computer system and method having a facility network architecture
US20030221086A1 (en) * 2002-02-13 2003-11-27 Simovich Slobodan A. Configurable stream processor apparatus and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692193A (en) * 1994-03-31 1997-11-25 Nec Research Institute, Inc. Software architecture for control of highly parallel computer systems
WO2001098871A2 (en) * 2000-06-19 2001-12-27 P.C. Krause And Associates, Inc. Distributed simulation
US20020169785A1 (en) * 2000-12-29 2002-11-14 Netemeyer Stephen C. Computer system and method having a facility network architecture
US20020133325A1 (en) * 2001-02-09 2002-09-19 Hoare Raymond R. Discrete event simulator
US20030221086A1 (en) * 2002-02-13 2003-11-27 Simovich Slobodan A. Configurable stream processor apparatus and methods

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Using Simulink Version 6", USING SIMULINK, XX, XX, June 2004 (2004-06-01), pages I - XVI,1, XP002383210 *
BELA CSUKAS ET AL: "Generic Bi-Layered Net Programming", IFIP CONFERENCE ON ARTIFICIAL INTELLIGENCE APPLICATIONS AND INNOVATIONS (AIAI), X, XX, vol. 187, 7 September 2005 (2005-09-07), pages 701 - 710, XP009091653 *
CSUKÁS B ET AL: "GENERIC BI-LAYERED NET, AS THE NATURAL COMPUTATIONAL MODEL OF CONSERVATION AND INFORMATION PROCESSES", INTERNATIONAL JOURNAL OF SIMULATION. SYSTEMS, SCIENCE AND TECHNOLOGY, UK SIMULATION SOCIETY, NOTTINGHAM, GB, vol. 6, no. 6, 2004, pages 10 - 22, XP007903366, ISSN: 1473-8031 *
GYOENGYI BANKUTI AND BELA CSUKAS: "Generic Bi-Layered Net Model. General Methodology for Process Simulation", IFIP CONFERENCE ON ARTIFICIAL INTELLIGENCE APPLICATIONS AND INNOVATIONS (AIAI), X, XX, vol. 187, 7 September 2005 (2005-09-07), pages 691 - 700, XP009091652 *

Also Published As

Publication number Publication date
HU0600034D0 (en) 2006-03-28
WO2007080437A9 (en) 2008-01-10
WO2007080437A2 (en) 2007-07-19

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