WO2009158679A8 - Shader interfaces - Google Patents

Shader interfaces Download PDF

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Publication number
WO2009158679A8
WO2009158679A8 PCT/US2009/048960 US2009048960W WO2009158679A8 WO 2009158679 A8 WO2009158679 A8 WO 2009158679A8 US 2009048960 W US2009048960 W US 2009048960W WO 2009158679 A8 WO2009158679 A8 WO 2009158679A8
Authority
WO
WIPO (PCT)
Prior art keywords
shader
registers
hlsl
shaders
complex
Prior art date
Application number
PCT/US2009/048960
Other languages
French (fr)
Other versions
WO2009158679A2 (en
WO2009158679A3 (en
Inventor
Michael V. Oneppo
Craig Peeper
Andrew L. Bliss
John L. Rapp
Mark M. Lacey
Original Assignee
Microsoft Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corporation filed Critical Microsoft Corporation
Priority to EP09771210.3A priority Critical patent/EP2289050B1/en
Priority to CN200980124880.0A priority patent/CN102077251B/en
Publication of WO2009158679A2 publication Critical patent/WO2009158679A2/en
Publication of WO2009158679A3 publication Critical patent/WO2009158679A3/en
Publication of WO2009158679A8 publication Critical patent/WO2009158679A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4488—Object-oriented
    • G06F9/449—Object-oriented method invocation or resolution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/541—Interprogram communication via adapters, e.g. between incompatible applications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/50—Lighting effects
    • G06T15/80—Shading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware

Abstract

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
PCT/US2009/048960 2008-06-27 2009-06-26 Shader interfaces WO2009158679A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP09771210.3A EP2289050B1 (en) 2008-06-27 2009-06-26 Shader interfaces
CN200980124880.0A CN102077251B (en) 2008-06-27 2009-06-26 Shader interfaces

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/163,734 2008-06-27
US12/163,734 US8581912B2 (en) 2008-06-27 2008-06-27 Dynamic subroutine linkage optimizing shader performance

Publications (3)

Publication Number Publication Date
WO2009158679A2 WO2009158679A2 (en) 2009-12-30
WO2009158679A3 WO2009158679A3 (en) 2010-05-06
WO2009158679A8 true WO2009158679A8 (en) 2010-11-18

Family

ID=41445370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/048960 WO2009158679A2 (en) 2008-06-27 2009-06-26 Shader interfaces

Country Status (4)

Country Link
US (3) US8581912B2 (en)
EP (1) EP2289050B1 (en)
CN (1) CN102077251B (en)
WO (1) WO2009158679A2 (en)

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Also Published As

Publication number Publication date
US20090322751A1 (en) 2009-12-31
US9824484B2 (en) 2017-11-21
EP2289050A4 (en) 2012-01-11
US9390542B2 (en) 2016-07-12
US20170039754A1 (en) 2017-02-09
EP2289050A2 (en) 2011-03-02
CN102077251B (en) 2014-01-08
US20140063029A1 (en) 2014-03-06
EP2289050B1 (en) 2019-12-04
CN102077251A (en) 2011-05-25
WO2009158679A2 (en) 2009-12-30
WO2009158679A3 (en) 2010-05-06
US8581912B2 (en) 2013-11-12

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